Hailong Yao

Multilevel Routing With Redundant Via Insertion

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant via addition. In addition, a rvia-driven maze routing algorithm is also integrated in the system to improve the insertion of redundant vias. Finally a redundant via placement heuristic is adopted to enhance the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing system. Besides much enhancement obtained in the aspect of redundant via placement, the system also obtains high routing completion rate, minimized total wire length and total number of vias in satisfactory runtime

Layout Decomposition Approaches for Double Patterning Lithography

In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45 nm test-cases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.

Efficient process-hotspot detection using range pattern matching

In current manufacturing processes, certain layout configurations are likely to have reduced yield and/or reliability due to increased susceptibility to stress effects or poor tolerance to certain processes like lithography. These problematic layout configurations need to be efficiently detected and eliminated from a design layout to enable better yield. In this paper, such layout configurations are called process-hotspots and an efficient and scalable algorithm is proposed to detect such process-hotspots in a given layout. The concept of a range pattern is introduced and used to accurately and compactly represent these process-hotspots. This representation is flexible and can incorporate information about the deficiencies of available modeling and/or subsequent correction (for instance, mask synthesis) techniques. Each range pattern can also be associated with a scoring mechanism to score the problem regions according to yield impact. A library of range patterns is being developed in collaboration with a fab. The proposed process-hotspot detection system assumes that process-hotspots are specified as a library of range patterns and determines all occurrences of any of these range patterns in a layout. It is fast and accurate and can be applied to large industrial layouts. Unlike previous work, the proposed scheme can identify problems that cannot be efficiently modeled or corrected by subsequent mask synthesis techniques and can thereby complement existing work in that area. Experimental results are quite promising and show that all locations that match a range pattern in a given layout can be found in a matter of minutes

Improved multilevel routing with redundant via placement for yield and reliability

This paper presents an improved multilevel Full-chip routing system which integrates global routing and detailed routing algorithms to achieve great enhancement in yield and reliability considering the redundant via placement. The system features a pre-coarsening stage which is equipped with a fast congestion-driven L-pattern global routing followed by the rvia-driven detailed routing. The L-pattern global routing benefits a lot to the reduction of vias and thus relieves the burden of redundant via addition. Then the rvia-driven maze routing algorithm considers the addition of redundant vias during routing. Finally the redundant via placement heuristic also contributes to improve the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing framework. The experimental results are promising.

Efficient range pattern matching algorithm for process-hotspot detection

As very large scale integration (VLSI) technology advances to smaller and smaller nodes, certain layout configurations tend to have reduced yield and/or reliability during manufacturing processes because of increased susceptibility to stress effects or poor tolerance to certain processes like lithography. Such layout configurations are called process-hotspots, which are represented here accurately and compactly by range patterns. The concept of a range pattern is introduced to represent a set of similar patterns compactly. Since low-yielding patterns are directly represented, it can supplement the deficiencies of available modelling and/or subsequent correction (for instance, mask synthesis) techniques. A scoring mechanism can be provided for each range pattern to score the problem regions covered by the range pattern according to their yield impact. A library of range patterns for representing the process-hotspots is being developed in collaboration with a semiconductor manufacturing company. A fast and accurate process-hotspot detection system based on the range pattern matching algorithm is implemented, which can find all occurrences of the process-hotspots represented as range patterns in a given industrial layout. Experimental results are quite promising and show that all the locations that match each range pattern (i.e. process-hotspots) in a given layout can be found in several minutes.

SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography

In triple patterning lithography (TPL), balanced feature density on each layout mask helps facilitate the following OPC process. This paper presents the first spacing uniformity-aware layout decomposition method, called SUALD, which formulates the density optimization problem in TPL based on the spacings between locally adjacent features on each colored layout mask, and hence enhances the patterning quality. Based on the new density formulation, a spacing uniformity graph is built using the Voronoi diagram. An effective heuristic triple partitioning algorithm is also proposed for TPL layout decomposition. Experimental results are very promising and show that SUALD obtains 69% and 40% improvements in average in the presented density metrics over an integer linear programming method without density control.

PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips

In flow-based microfluidic biochips, microvalves on the control layer need to be connected to control pins via control channels. In application-specific and portable microfluidic devices, critical microvalves need to switch at the same time for correct functionality. Those microvalves are required to have equal or similar channel lengths to the control pin, so that the control signal can reach them simultaneously. This paper presents a practical control-layer routing flow (PACOR) considering the critical length-matching constraint. Major features of PACOR include: (1) effective candidate Steiner tree construction and selection methods for multiple microvalves based on the deferred-merge embedding (DME) algorithm and maximum weight clique problem (MWCP) formulation, (2) minimum cost flow-based formulation for simultaneous escape routing for improved routability, and (3) minimum-length bounded routing method to detour paths for length matching. Computational simulation results show effectiveness and efficiency of PACOR with promising matching results and 100% routing completion rate.

Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips

This article presents the first flow-control codesign methodology, which seamlessly integrates both flow-layer and control-layer design stages. Experimental results show that the proposed codesign flow achieves notable improvements over the regular design framework with separate design stages.

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits

In analog and mixed signal designs, exact matching requirement is critical for correct functionality of analog devices. However, due to the excessive complexity, it is difficult to consider exact matching constraint in detailed routing stage. This paper presents a novel gridless detailed routing algorithm, which efficiently obtains the optimized detailed routing solutions for a given set of nets with exact matching constraints. The gridless routing algorithm is based on an efficient non-uniform grid model, which enables the obstacles avoidance. To verify the effectiveness of the gridless routing algorithm, a grid routing algorithm and a modified exact matching routing algorithm from [5] are also implemented. Experimental results show significant improvements of the proposed gridless routing algorithm over the other two algorithms in both QOR and runtime.

Revisiting the linear programming framework for leakage power vs. performance optimization

This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgate-biasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation - in every slew-load condition - between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-Lgate and Lgate-biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.