Xianlong Hong

Corner block list: an effective and efficient topological representation of non-slicing floorplan

In this paper, a corner block list-a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a corner block list, it takes only linear time to construct the floorplan. Unlike the O-tree structure, which determines the exact floorplan based on given block sizes, corner block list defines the floorplan independent of the block sizes. Thus, the structure is better suited for floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks and the aspect ratio of the chip are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising.

Interconnection driven VLSI module placement based on quadratic programming and considering congestion using LFF principles

In VLSI module placement interconnection behavior becomes increasingly important. Less flexibility first (LFF) principle is derived from human accumulated experience. An interconnection driven VLSI module placement algorithm based on LFF principles is proposed in this paper. We first use quadratic programming to optimize the total wire-length of the placement and then using a deterministic recursive partition rectangle packing algorithm based on LFF principles with consideration of congestion to implement the placement in an estimated fixed die area. Experimental results show efficiency and effectiveness of the proposed method.

Performance-Driven Steiner Tree Algorithms for Global Routing

This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal. One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree. A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms. Experiment results are given to demonstrate the effectiveness of the two algorithms.

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits

Thermal issues are a primary concern in the three-dimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D floorplanning, significantly increasing optimization complexity. Most existing floorplanners use combinatorial stochastic optimization techniques, hampering performance and scalability when used for 3D floorplanning. In this work, we propose and evaluate a scalable, temperature-aware, force-directed fioorplanner called 3D-STAF. Force-directed techniques, although efficient at reacting to physical information such as temperature gradients, must eventually eliminate overlap. This can cause significant displacement when used for heterogeneous blocks. To smooth the transition from an unconstrained 3D placement to a legalized, layer-assigned floorplan, we propose a three-stage force-directed optimization flow combined with new legalization techniques that eliminate white spaces and block overlapping during multi-layer floorplanning. A temperature-dependent leakage model is used within 3D-STAF to permit optimization based on the feedback loop connecting thermal profile and leakage power consumption. 3D-STAF has good performance that scales well for large problem instances. Compared to recently published 3D floorplanning work, 3D-STAF improves the area by 6%, wire length by 16%, via count by 22%, peak temperature by 6% while running nearly 4times faster on average.

Area minimization of power distribution network using efficient nonlinear programming techniques

This paper deals with area minimization of power network for very large-scale integration designs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. During the optimization, a penalty method, conjugate gradient method, circuit sensitivity analysis, and merging adjoint networks are applied, which enables the algorithm to optimize large circuits. The experiment results prove that this algorithm is robust and can achieve the objective of minimizing the area of power network in a short runtime.

A new congestion-driven placement algorithm based on cell inflation

In this paper, we describe a new congestion-driven placement based on cell inflation. In our approach, we have used the method of probability- estimation to evaluate the routing of nets. We also take use of the strategy of cell inflation to eliminate the routing congestion. Further reduction in congestion is obtained by the scheme of cell moving. We have tested our algorithm on a set of sample circuits from American industry and the results obtained have shown great improvement of routability.

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

An O ( n log n ) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane

Routing is one of the important phases in VLSI/ULSI physical design. The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is an essential part of routing since macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase. Efficient OARSMT algorithms can be employed in practical routers iteratively. Recently, IC routing and related researches have been extended from Manhattan architecture (λ2-geometry) to Y- / X-architecture (λ3- / λ4-geometry) to improve the chip performance. This paper presents an O(nlogn) heuristic, λ-OASMT, for obstacle-avoiding Steiner minimal tree construction in the λ-geometry plane. Based on obstacle-avoiding constrained Delaunay triangulation, a full connected tree is constructed and then embedded into λ-OASMT by a novel method called zonal combination. To the best of our knowledge, this is the first work addressing the λ-OASMT problem. Compared with two most recent works on OARSMT problem, λ-OASMT obtains up to 30Kx speedup with an even better quality solution. We have tested randomly generated cases with up to 1K terminals and 10K rectilinear obstacles within 3 seconds on a Sun V880 workstation (755MHz CPU and 4GB memory). The high efficiency and accuracy of λ-OASMT make it extremely practical and useful in the routing phase, as well as interconnect estimation in the process of floorplanning and placement.

Partitioning-based approach to fast on-chip decap budgeting and minimization

This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in todays VLSI physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But it adopts several new techniques, which significantly improve the efficiency of the optimization process. First, the new approach applies the time-domain merged adjoint network method for fast sensitivity calculation. Second, an efficient search step scheme is proposed to replace the time-consuming line search phase in conventional conjugate gradient method for decap budget optimization. Third, instead of optimizing an entire large circuit, we partition the circuit into a number of smaller sub-circuits and optimize them separately by exploiting the locality of adding decaps. Experimental results show that the proposed algorithm achieves at least 10X speed-up over the fastest decap allocation method reported so far with similar or even better budget quality and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations.

An Efficient Timing-Driven Global Routing Algorithm

In this paper, we propose an efficient timing-driven global routing algorithm. Unlike other conventional global routing techniques, interconnection delays are modeled and included during routing and rerouting process in order to minimize the routing area as well as to satisfy timing constraint. The timing-driven global routing problem is formulated as a multiterminal, multicommodity flow problem with integer flows and additional timing constraint. Two efficient timing-driven Steiner tree approach and one Steiner tree improving approach have been used to create initial routing results and reroute trees respectively. The algorithm has been implemented and the experimental results are quite promising.