Haissam Ziade

Analysis of experimental results on functional testing and diagnosis of complex circuits

A number of functional-level test approaches for microprocessors have been proposed. The GAPT approach, presented here, is a pragmatic one, but it is supported by a set of tools and experimental results. The authors describe the GAPT approach in detail. They draw tentative conclusions with respect to the effectiveness and scope of these functional test generation methods.<<ETX>>

An optimal implementation on FPGA of a hopfield neural network

The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN) that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN) parallel architecture on a SRAM-based FPGA. Themain advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions.

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied

The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.

Tracking System using GPS, vision and 3D virtual Model

In order to improve the vehicle tracking quality in the cities and especially in urban area, the following article handles the correspondence between real and virtual images to find the closest virtual image to the real one. Real image are extracted from cameras equipped by a GPS system, together installed in the vehicle. Virtual images are extracted using a GPS from a database managed by 3D geographical information system (3D- GIS). It is known that GPS cannot give accurately the coordinates of a vehicle so it is necessary to use other kind of information using embedded sensors like camera. A way to compute a position using vision is to find the closest image in a 3D cartographical database which corresponds to the real one seen by the camera. Two methods are developed and tested with real data : the first method uses the Hough transform where each line corresponds to a point in the polar coordinate then we compare the image transformations. The second method is based on the Ransac fitting homography method. This method based on taking the two images real and virtual image, find the corners of each image using a harris corner detector, use the maximally correlated points to connect them, robustly fits a homography to a set of putatively matched image points, find the number of putatively matched image points that are called inliers and the greatest the number of inliers the closer is the virtual image to a real one. It uses homography, harris corner detector, and correlation functions. Results with real data are presented to illustrate performance of developed method.

A method and an automated tool to perform SET fault-injection on HDL-based designs

A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.

Hopfield associative memory on mesh

The associative Hopfield memory is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an algorithm for implementing the Hopfield ANN on mesh parallel architectures. A Hopfield ANN model involves two major operations; broadcasting a value to a set of processors and summation of values in a set of processors. The main advantage of this algorithm is a high performance and cost effectiveness. An iteration of an N-bit (neuron) Hopfield associative memory only requires O(logN) time, whereas other known algorithms in literature of similar topology require O(N) time. Moreover, the proposed algorithm is cost effective because only higher dimension architectures were reported to achieve a complexity of O(logN) such as hypercubes.

Fault tolerant Hopfield associative memory on torus

The associative Hopfield memory, is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on a torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architectures such as the hypercube without the added cost. It requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT (algorithm-based fault tolerance) method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed).

Top down IC failure analysis using an e-beam system coupled to a functional tester

Abstract A diagnosis system devoted to precise failure analysis of complex I.C. has been built-up by coupling an E-beam tester, a functional tester and a test program generator. A case study illustrates the approach efficiency and the tools flexibility.

SEU simulation by fault injection in PSoC device: Preliminary results

In this paper the consequences of SEU (Single Event Upset) faults on System on Chip devices (SOC) are studied. A PSOC microcontroller CY8C27643 manufactured by Cypress was chosen as a test vehicle. Fault injection sessions were performed using the so-called (Code Emulated Upset) approach in two different HW/SW environments. Obtained results put in evidence the potentially critical consequences of some of the faults occurring in the digital blocks when a matrix multiplication benchmark is being executed.