Rafic A. Ayoubi

An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition

This paper presents a power-gating structure that employs a staggered-phase damping technique for suppressing power and ground rails fluctuation and stabilization time during mode-transition. Two same type sleep devices coupled to two clusters in a single power domain are switched-on at different time instants such that the turn-on time of one of these is delayed by half the resonant oscillation period relative to the turn-on time of the other. The same can be generalized to plurality of clusters where one set of sleep devices switch at the first time instant and the other set switch at the said second time instant. This technique was evaluated in a 1-V 90-nm CMOS technology in the context of a 3-stage 16-bit Carry-Select-Adder (CSA) component, and compared with the parallel sleep transistor technique that is based on reducing the instantaneous excitation current. Results show that the present technique reduces peak noise by 33.2% compared to standard power-gating structure, and achieves a settling time reduction of 4.03× and 3.21× compared to standard and parallel sleep transistor power-gating structures, respectively.

An optimal implementation on FPGA of a hopfield neural network

The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN) that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN) parallel architecture on a SRAM-based FPGA. Themain advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions.

Efficient mapping algorithm of multilayer neural network on torus architecture

This paper presents a new efficient parallel implementation of neural networks on mesh-connected SIMD machines. A new algorithm to implement the recall and training phases of the multilayer perceptron network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube, without the added cost; it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.

Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield Neural Network (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non-fault-tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

An FPGA Implementation of a High Resolution Phase Shift Beamformer

In this work, an implementation of a high resolution phase shift beamformer on FPGA is presented. This implementation is based on the angle recording (AR) CORDIC algorithm and uses a fine precision 2-path floating point adder for an accurate computation of the phase shifts. A pipelined architecture is used to decrease the chip area requirements and to increase the throughput of the beamformer. The proposed approach is quantitatively evaluated by performing a comparison with am approach based on the Xilinx core generator modules. The results show that the proposed implementation outperforms the latter technique in terms of speed and area. The implemented beamformer could be used for acquiring 2D and 3D ultrasound medical images in real time.

A method and an automated tool to perform SET fault-injection on HDL-based designs

A fully automated fault-injection method is presented. It deals with transient faults resulting from the impact of energetic particles and it can be applied early at design phase, on any circuit for which the register transfer level model is available. Results issued from its application to an Artificial Neural Network benchmark application put in evidence the accuracy of the studied method to predict error rates due to transient faults generated by the radiation environment.

TALS: Trigonometry-based Ad-hoc Localization System for wireless sensor networks

Node localizations techniques are a critical part in many wireless sensor network (WSN) applications. There are several challenges for building an efficient localization system that is suitable for wireless sensor networks, mainly, reducing computational complexity and communication overhead. For example, solving an over constraint set of linear equations via least square approximations and utilizing square root operations are computationally intensive. Moreover, flooding techniques used for transmitting the locations of the anchors wastes bandwidth and energy. In this context, the Trigonometric based Ad-hoc Localization System (TALS) is an anchor-based range-based localization system that utilizes trigonometric identities and properties to compute the position of the node. TALS is designed to address the above challenges without deteriorating the quality of the estimates by taking advantage of redundancy and data fusion techniques. TALS is simulated and compared against popular localization techniques where it presented superiority against those techniques.

Hopfield associative memory on mesh

The associative Hopfield memory is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an algorithm for implementing the Hopfield ANN on mesh parallel architectures. A Hopfield ANN model involves two major operations; broadcasting a value to a set of processors and summation of values in a set of processors. The main advantage of this algorithm is a high performance and cost effectiveness. An iteration of an N-bit (neuron) Hopfield associative memory only requires O(logN) time, whereas other known algorithms in literature of similar topology require O(N) time. Moreover, the proposed algorithm is cost effective because only higher dimension architectures were reported to achieve a complexity of O(logN) such as hypercubes.

Fault tolerant Hopfield associative memory on torus

The associative Hopfield memory, is a very useful artificial neural network (ANN) that can be utilized in numerous applications. Examples include, pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper provides an efficient and fault tolerant algorithm for implementing the Hopfield ANN on a torus parallel architecture. The main advantage of this algorithm is fault tolerance, high performance, and cost effectiveness. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architectures such as the hypercube without the added cost. It requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions. Moreover, the developed algorithm has an added advantage over other known algorithms due to its fault tolerance feature, which is based on ABFT techniques. The main advantage of our ABFT (algorithm-based fault tolerance) method over other existing ABFT methods is its ability to detect and correct several faults without any additional hardware overhead (i.e. no extra row or column is needed).

An efficient implementation of multi-layer perceptron on mesh architecture

This paper presents a new efficient parallel implementation of multi-layer perceptron on mesh-connected SIMD machines. A new algorithm to implement the recall and training phases of the multi-layer perceptron network with back-error propagation is devised. The developed algorithm is much faster than other known algorithms of its class and comparable in speed to more complex architecture such as hypercube without the added cost; it requires O(1) multiplications and O(log N ) additions, whereas most others require O(N) multiplications and O(N) additions. The proposed algorithm maximizes parallelism by unfolding the ANN computation to its smallest computational primitives and processes these primitives in parallel.