Haitong Tian

A polynomial time triple patterning algorithm for cell based row-structure layout

As minimum feature size keeps shrinking, and the next generation lithography (e.g, EUV) further delays, double patterning lithography (DPL) has been widely recognized as a feasible lithography solution in 20nm technology node. However, as technology continues to scale to 14/10nm, DPL begins to show its limitations and usually generates too many undesirable stitches. Triple patterning lithography (TPL) is a natural extension of DPL to conquer the difficulties and achieve a stitch-free layout decomposition. In this paper, we study the standard cell based row-structure layout decomposition problem in TPL. Although the general TPL layout decomposition problem is NP-hard, in this paper we will show that for standard cell based TPL layout decomposition problem, it is polynomial time solvable. We propose a polynomial time algorithm to solve the problem optimally and our approach has the capability to find all stitch-free decompositions. Color balancing is also considered to ensure a balanced triple patterning decomposition. To speed up the algorithm, we further propose a hierarchical algorithm for standard cell based layout, which can reduce the run time by 34.5% on average without sacrificing the optimality. We also extend our algorithm to allow stitches for complex circuit designs, and our algorithm guarantees to find optimal solutions with minimum number of stitches.

Constrained pattern assignment for standard cell based triple patterning lithography

Triple patterning lithography (TPL) has been recognized as one of the most promising candidates for 14/10nm technology node. Apart from obtaining legal TPL decompositions, various concerns have been raised by the designers, among them consistently assigning the same pattern for the same type of standard cells and balancing the usage of the three masks are two most critical ones. In this paper, a hybrid approach (SAT followed by a sliding-window approach) is proposed targeting at these two problems. To assign the same pattern for the same type of standard cell, we pre-color the boundary polygons of each type of cell by solving a small SAT problem. Following that we propose a sliding-window based approach to compute a locally balanced decomposition. Our algorithm guarantees to find a feasible solution if one exists. Experimental results verify that the problem can be solved very efficiently with the proposed algorithm. Superior locally balanced decompositions are achieved compared with the previous approach in.

Directed Self-Assembly (DSA) Template Pattern Verification

Directed Self-Assembly (DSA) is a promising technique for contacts/vias patterning, where groups of contacts/vias are patterned by guiding templates. As the templates are patterned by traditional lithography, their shapes may vary due to the process variations, which will ultimately affect the contacts/vias even for the same type of template. Due to the complexity of the DSA process, rigorous process simulation is unacceptably slow for full chip verification. This paper formulate several critical problems in DSA verification, and proposes a design automation methodology that consists of a data preparation and a model learning stage. We present a novel DSA model with Point Correspondence and Segment Distance features for robust learning. Following the methodology, we propose an effective machine learning (ML) based method for DSA hotspot detection. The results of our initial experiments have already demonstrated the high-efficiency of our ML-based approach with over 85% detection accuracy. Compared to the minutes or even hours of simulation time in rigorous method, the methodology in this paper validates the research potential along this direction.

Triple patterning aware detailed placement with constrained pattern assignment

Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. There are various concerns for TPL decompositions. For standard cell based designs, assigning the same pattern for the same type of cells is a desired property for TPL decomposition. It is more robust for process variations and gives the chip similar physical and electrical characteristics as well as more reliable and predictable performance. Assigning the same type of pattern for the same type of cell is called a constrained pattern assignment (CPA) problem. In this paper, we integrated the flow of detailed placement and TPL decompositions with CPA coloring constraints. We focused on refining a layout to make it CPA-friendly during the detailed placement stage while minimizing the area and HPWL (half perimeter wire length) overhead. A weighted partial MAX SAT approach is proposed which guarantees to obtain a CPA-friendly detailed placement result while minimizing the area overhead. An efficient graph model is also proposed to compute the locations of the cells with optimal HPWL. Our formulation is very efficient and achieves a 79.4% area overhead reduction compared with the approach of fixing cell colors beforehand. Better HPWL are also achieved consistently over all benchmarks.

Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time

Self-aligned double patterning is one of the most promising double patterning techniques for sub-20nm nodes. As in any multiple patterning techniques, layout decomposition is the most important problem. In SADP decomposition, overlay is among the most primary concerns. Most of the existing works target at minimizing the overall overlay, while others totally forbid the overlay. On the other hand, most of the works either rely on exponential time methods, or apply heuristic that cannot guarantee to find a solution. In this paper, we consider the SADP decomposition problem in row-based standard cell layout, where the overlay violations are minimized. Although SADP decomposition has been shown to be NP-hard in general, we showed that it can be solved in polynomial time when the layout is row-based standard cells. We propose a polynomial time optimal algorithm that finds a decomposition with minimum overlay violations. The efficiency of our method is further demonstrated by the experimental results.

DSA template optimization for contact layer in 1D standard cell design

At the 7 nm technology node, the contact layers of integrated circuits (IC) are too dense to be printed by single exposure lithography. Block copolymer directed self-assembly (DSA) has shown its advantage in contact/via patterning with high throughput and low cost. To pattern contacts with DSA, guiding templates are usually printed first with conventional lithography, e.g., 193 nm immersion lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of controlling the DSA patterns inside, which have a finer resolution than the templates. The DSA contact pitch depends on the chemical property of block copolymer and it can be adjusted within a certain range under strong lateral confinement to deviate from the natural pitch. As a result, different patterns can be obtained through different parameters. Although the guiding template shapes can be arbitrary, the overlay accuracy of the contact holes patterned are different and largely depend on the templates. Thus, the guiding templates that have tolerable variations are considered as feasible, and those have large overlays are considered as infeasible. To pattern the contact layer in a layout with DSA technology, we must ensure that all the DSA templates in the layout are feasible. However, the original layout may not be designed in a DSA-friendly way. Moreover, the routing process may introduce contacts that can only be patterned by infeasible templates. In this paper, we propose an optimization algorithm that optimize the contact layer for DSA patterning in 1D standard cell design. In particular, the algorithm modifies the layout via wire permutation technique to redistribute the contacts such that the use of infeasible templates is avoided and the feasible patterns that with better overlay control are favored. The experimental result demonstrate the ability of the proposed algorithm in helping to reduce the design and manufacturing cost of a DSA-enabled process at 7 nm technology node.

An efficient linear time triple patterning solver

Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. In this paper, we applied triple patterning lithography on standard cell based designs, and proposed a novel algorithm to solve the problem. The algorithm guarantees to find a legal TPL decomposition with optimal number of stitches if one exists. A graph model is proposed to reduce the number of vertices in the solution graph, and a fast approach is developed to achieve simultaneous runtime and memory improvement. An efficient approach to limit the number of stitches is also proposed, which greatly reduces the total number of stitch candidates and enables an incremental implementation of the algorithm. Experimental results shows that the proposed algorithm is very efficient, which achieves 39.1% runtime improvement and 18.4% memory reduction compared with the state-of-the-art TPL algorithm on the same problem.

Hybrid lithography for triple patterning decomposition and E-beam lithography

As we advances into 14/10nm technology node, single patterning technology is far from enough to fabricate the features with shrinking feature size. According to International Technology Roadmap for Semiconductors in 2011,1 double patterning lithography is already available for massive productions in industry for sub-32nm half pitch technology node. For 14/10nm technology node, double patterning begins to show its limitations as it uses too many stitches to resolve the native coloring conflicts. Stitches will increase the manufacturing cost, lead to potential functional errors of the chip, and cause the yield lost. Triple patterning lithography and E-Beam lithography are two emerging techniques to beat the diffraction limit for current optical lithography system. In this paper, we investigate combining the merits of triple patterning lithography and E-Beam lithography for standard cell based designs. We devise an approach to compute a stitch free decomposition with the optimal number of E-Beam shots for row structure layout. The approach is expected to highlight the necessity and advantages of using hybrid lithography for advanced technology node.

Evaluation of cost-driven triple patterning lithography decomposition

As the current 193nm ArF immersion lithography technology is approaching its bottleneck, multiple patterning techniques have to be introduced to fulfill the process requirements in the sub-20nm technology node. Among all different patterning techniques, triple patterning lithography (TPL) is one of the major options for 14 nm or 10 nm technology node, which has a substantial requirement on process control and cost control at the same time. Patterning decomposition is the key step for the success of TPL. In the conventional TPL lithography, a constant spacing distance dmin is used to determine whether two nearby features should be on the same mask. However, in reality, the no-print and the best-print scenarios can never be separated by a clear constant number. Indeed, the decomposition criteria is closed related to lithography printing parameters, pattern types, and geometry distances. The conventional spacing rule with a constant number is way too simple. In this paper, we re-evaluate the conventional minimum spacing rule and utilize a local pattern cost model to evaluate our previous optimal TPL algorithm. Given a user specified local pattern aware cost model, our algorithm can easily embed the model into our formulation and compute an optimal solution. This demonstrates the extendability and robustness of our previous TPL algorithm.

Model-based multiple patterning layout decomposition

As one of the most promising next generation lithography technologies, multiple patterning lithography (MPL) plays an important role in the attempts to keep in pace with 10 nm technology node and beyond. With feature size keeps shrinking, it has become impossible to print dense layouts within one single exposure. As a result, MPL such as double patterning lithography (DPL) and triple patterning lithography (TPL) has been widely adopted. There is a large volume of literature on DPL/TPL layout decomposition, and the current approach is to formulate the problem as a classical graph-coloring problem: Layout features (polygons) are represented by vertices in a graph G and there is an edge between two vertices if and only if the distance between the two corresponding features are less than a minimum distance threshold value dmin. The problem is to color the vertices of G using k colors (k = 2 for DPL, k = 3 for TPL) such that no two vertices connected by an edge are given the same color. This is a rule-based approach, which impose a geometric distance as a minimum constraint to simply decompose polygons within the distance into different masks. It is not desired in practice because this criteria cannot completely capture the behavior of the optics. For example, it lacks of sufficient information such as the optical source characteristics and the effects between the polygons outside the minimum distance. To remedy the deficiency, a model-based layout decomposition approach to make the decomposition criteria base on simulation results was first introduced at SPIE 2013.1 However, the algorithm1 is based on simplified assumption on the optical simulation model and therefore its usage on real layouts is limited. Recently AMSL2 also proposed a model-based approach to layout decomposition by iteratively simulating the layout, which requires excessive computational resource and may lead to sub-optimal solutions. The approach2 also potentially generates too many stiches. In this paper, we propose a model-based MPL layout decomposition method using a pre-simulated library of frequent layout patterns. Instead of using the graph G in the standard graph-coloring formulation, we build an expanded graph H where each vertex represents a group of adjacent features together with a coloring solution. By utilizing the library and running sophisticated graph algorithms on H, our approach can obtain optimal decomposition results efficiently. Our model-based solution can achieve a practical mask design which significantly improves the lithography quality on the wafer compared to the rule based decomposition.