Hajime Yamazaki

Inhomogeneous GaAs FET Threshold Voltages Related to Dislocation Distribution

Clear correlation between dislocation distribution and FET threshold voltage distribution in undoped LEC GaAs was observed directly for the first time by automatic computer-controlled measurement of drain-source current (Ids) and threshold voltage (Vth). FETs fabricated in the high EPD area, which covers the center and the periphery of (100) wafers, showed high Ids and low Vth, whereas FETs fabricated in the low EPD area showed low Ids and high Vth.

Activation efficiency improvement in Si‐implanted GaAs by P co‐implantation

Co‐implantation effects of N, P, and As are studied for Si‐implanted GaAs by the Hall effect and photoluminescence measurements. The P co‐implantation enhances and homogenizes the activation efficiency of the implanted Si, and decreases photoluminescence peak intensities of the SiAs and the GaAs acceptors. It also suppresses the variation of the Si activation efficiency among the crystal ingots by half. These results indicate that P co‐implantation is a promising method for fabricating active layers of high‐performance GaAs large scale integrated circuits.

Annealing effect on the electrical properties of heavily C‐doped p+GaAs

The carrier concentration in heavily carbon‐doped p+‐GaAs epilayers (about 1.3×1020 cm−3) is decreased together with the mobility by annealing at temperatures of 700 °C or higher but not at temperatures of 600 °C or lower. In comparatively lightly C‐doped p+ epilayers (about 3.5×1019 cm−3), the carrier concentration is not decreased by annealing at temperatures from 500 to 850 °C. The deep photoluminescence peak at a wavelength of around 1080 nm accompanied by a hump at around 1420 nm are found only in heavily C‐doped epilayers; the wavelength of this peak is very close to that of the Ga vacancy −the C donor center. The photoluminescence intensity is increased by the annealing at 850 °C but not at 600 °C. The thermal behaviors of the deep photoluminescence levels can well explain those of carrier concentration and mobility if we consider the photoluminescence levels to be the index for the compensation centers.

Leakage Current IL Variation Correlated with Dislocation Density in Undoped, Semi-Insulating LEC-GaAs

Leakage current IL equivalent to sheet resistance was measured by the two-point probe method, and was directly correlated with dislocation density variation across (100) wafers of undoped, semi-insulating LEC-grown GaAs. It was found, for the first time, that leakage current IL variation corresponds closely to dislocation density.

Characterization of a thin Si‐implanted and rapid thermal annealed n‐GaAs layer

Very thin, high carrier concentration layers for high performance GaAs field‐effect transistors are realized by lamp annealing, combined with low‐energy (<30 keV) ion implantation. The characteristics of these thin layers are investigated by the Hall effect, capacitance‐voltage, photoluminescence, and secondary ion mass spectrometry (SIMS). The optimum temperature giving the maximum sheet carrier concentration is the result of a balance between damage recovery and acceptor generation. The optimum temperature decreases as the implantation energy is reduced. The effective implanted layer thicknesses obtained by SIMS are larger than the Lindhard–Scharff–Schiott calculated values. The minimum effective active layer thickness of 0.045 μm is obtained with a 10‐keV implanted sample. This value is about one‐half that obtained for the 30‐keV implanted furnace annealed sample.

Improvement of field‐effect transistor threshold voltage uniformity by using very low dislocation density liquid encapsulated Czochralski‐grown GaAs

Threshold voltage (Vth) uniformity in very low dislocation density liquid encapsulated Czochralski‐grown GaAs was investigated. A standard deviation (σVth) of 13 mV was realized for Vth from the center part of the etch pit free area on the wafer. No correlation was observed between Vth and the distance from a field‐effect transistor (FET) gate to its nearest neighbor etch pit. A σVth of 10 mV can be obtained by eliminating crystal dislocations and background fluctuations such as striations and also refining the FET fabrication process.

Effects of annealing ambient on the electrical properties in heavily C‐doped p+‐AlGaAs

The thermal behavior of the carrier concentration and the lattice constant in heavily carbon‐doped p+‐AlGaAs epilayers grown by metalorganic chemical vapor deposition are dramatically dependent on the annealing ambient at temperatures between 500 and 700 °C. Annealing in a hydrogen and arsine mixed gas ambient decreases the carrier concentration and increases the lattice constant. On the other hand, annealing in a hydrogen gas ambient increases the carrier concentration and decreases the lattice constant between 500 and 600 °C, which is consistent with our previous data for annealing in a nitrogen gas ambient. However, the carrier concentration after annealing at 700 °C is a little lower in hydrogen than in nitrogen. The above behavior of the carrier concentration and the lattice constant is well explained by incorporating and removing the hydrogen atoms in the epilayers during annealing.

Reduction of recombination centers in C‐doped p+‐GaAs/n‐AlGaAs heterojunctions by post‐growth annealing

The effect of post‐growth annealing at 500, 600, and 700 °C on the electrical characteristics of C‐doped p+‐GaAs/n‐AlGaAs junction diodes fabricated with metalorganic chemical vapor deposition layers has been investigated. Recombination current is reduced by post‐growth annealing at 600 and 700 °C, but not at 500 °C. The current reduction is primarily attributed to the dramatic reduction of 0.55 eV deep levels, which may be oxygen related complex levels. Under present annealing conditions, no degradation of carrier profiles near the p+‐n junction is detected. Thus, post‐growth annealing at temperatures of 600 °C or higher is a promising method for reducing recombination centers in the C‐doped p+‐GaAs/n‐AlGaAs junction.

Effect of oxygen‐implant isolation on the recombination leakage current of n‐p+ AlGaAs graded heterojunction diodes

The recombination leakage current induced by planar isolation of n‐p+AlGaAs graded heterojunction area with oxygen ion implantation followed by annealing at 500–650 °C has been investigated. The recombination leakage current is smaller than that induced by conventional isolation with hydrogen ion implantation; specifically, it is about one order of magnitude smaller after the higher temperature (600–650 °C) annealing. The main origin of the remaining recombination leakage current is probably not oxygen deep levels but rather recombination centers related to the ion implantation damage that remains after annealing. A point‐defect complex level, which may be related to the recombination center, is detected at an activation energy of around 0.8 eV by deep level transient spectroscopy.

ELECTRICAL AND OPTICAL PROPERTIES OF OXYGEN-ION HOT-IMPLANTED GAAS LAYERS

Oxygen‐ion hot implantation into undoped GaAs has been investigated as fundamental research for the purpose of fabricating highly resistive isolation regions at lower temperatures. Hot implantation at 300 °C at an energy of 170 keV and a dose of 1×1015 cm−2 results in a sheet resistivity of 4×106 Ω/⧠ without post‐implant annealing and 7.7×106 Ω/⧠ after annealing at 400 °C for 10 min. These values are about one order of magnitude higher than those obtained after implantation at the same energy and dose done at room temperature. This high resistivity of the hot‐implanted layers is caused by both the removal of hopping conduction with an activation energy of 0.06 eV and the formation of 0.24–0.27 eV deep‐level electron traps. The effective reduction in implantation damage resulting from hot implantation, which induces the removal of hopping conduction, is confirmed by laser Raman spectroscopy.