Kimiyoshi Yamasaki

Deep Level Transient Spectroscopy of Bulk Traps and Interface States in Si MOS Diodes

Deep-leve transient spectroscopy (DLTS) of bulk traps and interface states in Si MOS diodes are theoretically studied and energy levels, capture cross-sections and spatial and energy density distributions of majority-carrier traps are measured. In P+-implanted unannealed MOS diodes, four bulk traps are measured at Ec-0.18 eV, Ec-0.20 eV, Ec-0.31 eV and Ec-0.45 eV. Their spatial distributions are found to be the same among them within experimental error and thought to be corresponding to the distribution of implanted ions qualitatively. Bulk traps are distinguished from interface states experimentally. The capture cross-section of interface states in non-implanted MOS diodes are measured to be of the order of 10-16 cm2 in the energy range of Ec-0.15 eV to Ec-0.30 eV. The interface state density measured with DLTS is found to be in a reasonable agreement with those detetmined by other methods.

Determination of the interface states in GaAs MOS diodes by deep‐level transient spectroscopy

The capture cross sections and density‐energy distribution of the trap states at the interface between GaAs epitaxial layers and oxide films grown by anodization in oxygen plasma have been determined by deep‐level transient spectroscopy (DLTS). The capture cross sections are of the order of 10−12–10−13 cm2. The state density in the energy space range from 1×1013 to 3×1013 cm−2 eV−1. It has a peak 0.43 eV below the conduction band edge, but increases again near the valence band edge. The existence of traps in the oxide is also suggested. The activation energies of the emission rates determined by constant‐capacitance DLTS with a small pulse voltage are in good agreement with the surface potentials, and no particular band structure at the interface, such as an interface band, has been found.

Characterization of a thin Si‐implanted and rapid thermal annealed n‐GaAs layer

Very thin, high carrier concentration layers for high performance GaAs field‐effect transistors are realized by lamp annealing, combined with low‐energy (<30 keV) ion implantation. The characteristics of these thin layers are investigated by the Hall effect, capacitance‐voltage, photoluminescence, and secondary ion mass spectrometry (SIMS). The optimum temperature giving the maximum sheet carrier concentration is the result of a balance between damage recovery and acceptor generation. The optimum temperature decreases as the implantation energy is reduced. The effective implanted layer thicknesses obtained by SIMS are larger than the Lindhard–Scharff–Schiott calculated values. The minimum effective active layer thickness of 0.045 μm is obtained with a 10‐keV implanted sample. This value is about one‐half that obtained for the 30‐keV implanted furnace annealed sample.

Three-dimensional passive circuit technology for ultra-compact MMICs

A novel passive circuit technology of a three-dimensional (3D) metal-insulator structure has been developed for ultra-compact MMICs. By combining vertical passive elements, such as a wall-like microwire for shielding or coupling and a pillar-like via connection, with multilayer passive circuits, highly dense and more functional MMICs can be implemented. >

Anodic Oxidation of GaAs Using Oxygen Plasma

Anodic oxidation of GaAs using oxygen plasma, produced by high-frequency (420kHz) electrodeless discharge in oxygen with the pressure of about 0.1–0.3 torr, has been carried out. A GaAs chip was located outside the plasma generating region in order to keep its temperature below 300°C. Positive voltage of 10–100 V with respect to the plasma was applied to the chip. The oxidation rate K is proportional to the dc current, and depends on the position and temperature of the chip, and on the oxygen pressure, but neither on the carrier concentration (1016–1018 cm-3) nor on the surface orientation. The oxidation rate is represented by K=4.2×10-4exp [q(-1.5+4.4×10-7Eox)/kT] (cm/s), where the electric field in the oxide Eox is in V/cm. The current efficiency is about 10–50%. The oxide is uniform and glassy, readily dissolved in acids and alkalis and slowly attacked by hot water. No change of oxide thickness by heat treatment is observed up to 500°C. The C-V characteristics of MOS capacitors show the injection-type hysteresis and frequency dispersion in the so-called accumulation region, especially those for n-type substrate.

A 0.1-/spl mu/m self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs

We have developed the technologies to fabricate about 0.1-/spl mu/m-gate-length GaAs MESFETs with a multilayer interconnection structure. We fabricated excellent high-frequency performance of a 0.06-/spl mu/m-gate-length MESFET having current-gain cutoff frequency (f/sub T/) of 168 GHz. Using 0.13-/spl mu/m-gate-length MESFETs, we also fabricated an ultra-high-speed decision circuit operating up to 32 Gbit/s.

Multigigabit multichannel optical interconnection module for broadband switching system

This paper describes optical transmitter and receiver modules for package-to-package interconnection in broadband switching networks such as an asynchronous transfer mode switch fabric. These modules, which include the multiplexer and demultiplexer, can reduce the number of connections and the problem of skew between links. Five-channel optical transmitter and receiver modules were fabricated and demonstrated at 2.8 Gbit/s with a power dissipation of 4.5 W per channel. Moreover, temperature-insensitive optical interconnection was successfully demonstrated by driving a laser with a constant bias current over the threshold and by deducting the optical signal offset. The output power of the transmitter module was -4.2 dBm. Nonuniformity of the transmitter output powers across the range of optical channels was 250 m. >

Phosphorus coimplantation effects on optimum annealing temperature in Si‐implanted GaAs

Phosphorus (P) coimplantation raises the optimum annealing temperature, providing maximum sheet carrier concentration in Si‐implanted GaAs active layers. 3×1013 cm−2 coimplanted P raises the optimum annealing temperature for channel layers from 920 to 990 °C, the same temperature for contact layers. Photoluminescence measurement reveals that this is due to suppression of GaAs and SiAs acceptor generations up to about 1000 °C by P coimplantation. These features indicate that P coimplantation helps to achieve GaAs integrated circuits with high performance.

EB-Writing n + self-aligned GaAs MESFETs for high-speed LSIs

Electron-beam direct writing has been applied to the fabrication of n+self-aligned (SAINT) GaAs MESFETs for high speed LSIs in order to achieve very short gate length below a half micrometer. In this application, position deviation due to semi-insulating substrate charge-up has been completely avoided by using a newly developed multilayer resist in which thin metal film is inserted. The short channel effects have been successfully reduced by decreasing the thickness of the n+-layers. As the result, an extremely fast switching speed of 16.7 ps/gate has been obtained at room temperature from a ring oscillator with 0.3 µm gate length SAINT FETs.

High On/Off Current Ratio p-InGaN/AlGaN/GaN HEMTs

An excellent on/off current ratio of 1010 and a nearly ideal subthreshold slope of 65 mV/dec was confirmed in a p-InGaN/AlGaN/GaN high-electron-mobility transistor. Favorable I-V characteristics were achieved with the p-InGaN cap layer under the gate electrode. A dry etching technique with a low-damage p-InGaN cap layer resulted in a significantly low leakage current of 10-11 A/mm.