Haksun Lee

Characterization and Estimation of Solder-on-Pad Process for Fine-Pitch Applications

Popular solder-bumping mechanisms such as electroplating and stencil printing suffer from either high process costs or technical limitations. A low-cost solder-on-pad (SoP) process has been developed to meet the requirements of fine-pitch solder bumping. This paper focuses on the characterization and estimation of the SoP process. To form a solder bump without soldering defects, optimum process conditions should be carefully designed. A model to estimate the bump volume and predict the bump height is suggested. By optimizing the composition of solder paste material called solder-bump-maker, and by adjusting the process conditions, Sn-Ag-Cu solder bumps with different heights are obtained. The experiments and analysis to understand the impact of parameters were based on test vehicles with 80 μm pitch size. Then, the measured heights of solder bumps are compared with the model to see how they fit the estimation. Finally, a similar process has been conducted to test vehicles with pitch sizes of 150 and 40 μm, to confirm the scalability of the SoP process in different pitch sizes.

Characterization of 3D stacked high resistivity Si interposers with polymer TSV liners for 3D RF module

The material designs of the Si interposers are optimized for a 3D RF module. The high resistivity Si wafers are used for the Si interposer fabrication: 1,000 Ω·cm ~ 10,000 Ω·cm. To reduce the capacitance and mechanical stress between Cufilled TSV and Si substrate, a polyimide insulation layer is applied as a TSV liner. We designs several types of the transmission line structures and measures their electrical properties. For the 3D interconnection between the Si interposers, fluxing underfill material is developed and used as a pre-applied underfill for the thermocompression bonding process. With these optimizations of materials design of the Si interposers, the microstrip line shows the electrical loss of 0.065 dB/mm at 10 GHz, and the insertion loss of the vertical transition is 0.4 dB at 10 GHz.

Development of low contact resistance interconnection for display applications

This paper focuses on development of a low contact resistance interconnection for low temperature bonding applications. Alternative to conventional display interconnection mechanisms using anisotropic conductive film (ACF), solder and underfill method using low melting point Bi58-Sn solder is suggested. Solder bumping is carried out using a maskless Solder-on-Pad technology. An average bump height of 16.4μm with 80μm bump pitch is achieved by optimizing the solder paste material called Solder-Bump-Maker. The test vehicle with bumps is flip chip bonded with a top die using Fluxing underfill. In order to analyze the quality of the bonded interconnection, contact resistance was measured using the 4-point probe method, and a moisture absorption test was conducted in a 85°C/85% relative humidity condition for 100 hours. The contact resistance values before and after the reliability test show no significant difference, which demonstrates that the suggested interconnection is a robust joint with increased electrical performance.

Maskless screen printing technology for 20μm-pitch, 52InSn solder interconnections in display applications

Traditionally, ACF (Anisotropic Conductive Adhesive) technology has been used for CoG (Chip-on-Glass) and FoG (Flex-on-Glass) interconnections in display packaging area. The electrical contacts of ACF technology are based on the mechanical contacts between the electrodes on substrates and conductive particles in ACF. As pitches of these interconnections tend to get finer than 30 μm and bonding temperature needs to be decreased because of warpage concerns during the bonding process, a novel interconnection technology for the advanced display systems is necessary. In this paper, a maskless screen printing technology is proposed to form and bond 20 μm-pitch, 52InSn solder interconnections for advanced display systems. InSn solder is selected to decrease the bonding temperature because its melting point is 118°C. A novel material, called as solder bump maker (SBM) is developed to have InSn solder powder in SBM used for InSn bumping process. The polymer matrix and deoxidizing agent in SBM are carefully designed to make InSn solder powder in SBM wet on Cu or Au electrodes on a substrate during the bumping process. Since InSn solder powder resides only on electrodes on a substrate with temperature variations because of the surface tensions between the solder powder and metal electrodes, a maskless screen printing process can be adopted for the InSn, fine-pitch bumping process. Using a maskless screen printing process with SBM, 20 μm-pitch, InSn solder interconnections on a glass substrate are successfully formed. We, also, developed a no-flow underfill material, name as fluxing underfill, for a bonding material of InSn interconnections. It plays roles of flux and underfill at the same time during the bonding process. The bonding process for 20 μm-pitch, InSn solder interconnections is successfully achieved using fluxing underfill. Its peak temperature of the bonding process is 130°C.

Design of Low-Profile Integrated Transformer and Inductor for Substrate-Embedding in 1-5kW Isolated GaN DC-DC Converters

This paper presents the design analysis of low-profile transformers in 1-5kW DC-DC resonant converters. Recent advances in GaN devices are expected to improve the efficiency and power density of power converters, while the magnetics still remain the major bottleneck to miniaturization. A low-profile integrated magnetic component design that enables low-loss and high-power density is proposed for 400V/48V DC-DC resonant converters with 1kW output power. The winding loss, core loss, and power density of the novel magnetic component design is analyzed and compared with the conventional design approach using planar cores. Higher power density and lower loss are demonstrated with the novel design approach.

Characterization of hybrid underfill for low-temperature process applicable to flexible substrate

As the interests in wearable devices are become growing, flexible substrates is being extensively investigated. In this study, new hybrid underfill for a low temperature process to create an electrical interconnection system on flexible substrate was studied. Hybrid underfill material is composed with underfill materials and 54Bi27In19Sn solder powder which has melting temperature at 83°C. For the stable chemical reaction, process temperature was set to 130°C. Hybrid underfill material has advantage of reducing processing step because the processing step such as solder joint formation, fluxing, cleaning, underfill step can proceed at a time. To optimize the wettability of solder powder, compositions and the ratio or the materials and processing conditions are controlled. By controlling the various conditions such as reductant and catalyst of hybrid underfill material, we optimize the low temperature process. As a result, solder joint is formed stably at a low temperature.