Hamid Hadim
Stevens Institute of Technology
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Featured researches published by Hamid Hadim.
Nanotechnology | 2010
Weihe Xu; Yong Shi; Hamid Hadim
The P-type perovskite oxides La(1-x)Sr(x)CoO(3) are a promising group of complex oxide thermoelectric (TE) materials. The thermoelectric properties of these oxides are expected to be significantly improved when their critical dimensions are reduced to the nanoscale. In this paper, the La(0.95)Sr(0.05)CoO(3) nanofibers, with diameters in the range of approximately 35 nm, were successfully prepared by the electrospinning process. X-ray diffraction (XRD) and scanning electron microscopy (SEM) were used to characterize these thermoelectric nanofibers. A micro-electromechanical (MEMS) tester was designed and fabricated to measure the Seebeck coefficient of the nanofibers. The measured voltage output was as large as 1.7 mV and the obtained Seebeck coefficient of the nanofibers reached 650 microV K(-1).
IEEE Transactions on Advanced Packaging | 2007
Tohru Suwa; Hamid Hadim
A new multidisciplinary design and optimization methodology in electronics packaging is presented. A genetic algorithm combined with multidisciplinary design and multiphysics analysis tools are used to optimize key design parameters. This methodology is developed to improve the electronic package design process by performing multidisciplinary design and optimization at an early design stage. To demonstrate its capability, the methodology is applied to a ball grid array (BGA) package design. Multidisciplinary criteria including thermal, thermal strain, electrical, electromagnetic leakage, and cost are optimized simultaneously. A simplified routability analysis criterion is used as a constraint. The genetic algorithm is used for systematic design optimization. The present methodology can be applied to electronics product design at various packaging levels.
Journal of Electronic Packaging | 2007
Tohru Suwa; Hamid Hadim
A multidisciplinarv placement optimization methodology for heat generating electronic components on printed circuit boards (PCBs) is presented. The methodology includes thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location which are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology which is based on a combination of a superposition method and artificial neural networks is developed for this study. Two genetic algorithms with different thermal prediction modules are used in a cascade in the optimization process. The first genetic algorithm uses simplified thermal network modeling and it is mainly aimed at finding component locations that avoid any overlap. Compact thermal models are used in the second genetic algorithm leading to more accurate thermal prediction which Improves the placement optimization obtained using the first algorithm. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate its capabilities, the present methodology is applied to a test case involving placement optimization of several heat generating electronics components on a PCB.
IEEE Transactions on Components and Packaging Technologies | 2007
Tohru Suwa; Hamid Hadim
A multidisciplinary placement optimization methodology for heat generating electronic components on a printed circuit board (PCB) subjected to forced convection in an enclosure is presented. In this methodology, thermal, electrical, and placement criteria involving junction temperature, wiring density, line length for high frequency signals, and critical component location are optimized simultaneously using the genetic algorithm. A board-level thermal performance prediction methodology based on channel flow forced convection boundary conditions is developed. The methodology consists of a combination of artificial neural networks (ANNs) and a superposition method that is able to predict PCB surface and component junction temperatures in a much shorter calculation time than the existing numerical methods. Three ANNs are used for predicting temperature rise at the PCB surface caused by a single heat source at an arbitrary location on the board, while temperature rise due to multiple heat sources is calculated using a superposition method. Compact thermal models are used for the electronic components thermal modeling. Using this optimization methodology, large calculation time reduction is achieved without losing accuracy. To demonstrate its capabilities, the present methodology is applied to a test case involving multiple heat generating component placement optimization on a PCB.
Journal of Electronic Packaging | 2008
Hamid Hadim; Tohru Suwa
Electronics packaging design is a process that requires optimized solutions based on multidisciplinary design trade-offs, which usually have complex relationships among multiple design variables. Required numerical analyses combining electrical, thermal, and thermomechanical, among others, have made the multidisciplinary design and optimization process more challenging because of their time-intensive modeling and computation. In this paper, a state-of-the-art review of recent multidisciplinary design and optimization methodologies in electronics packaging is presented. The reported methodologies are divided into three groups: (1) integrated multidisciplinary computer aided design (CAD) environment, (2) semi-automated design optimization techniques, and (3) automated component placement techniques. In the first group, multidisciplinary design and optimization are carried out using interactive CAD environment software. The electronics packaging designer inputs data and makes decisions, while the CAD software provides a comprehensive multidisciplinary modeling and simulation environment. In the second group, using semi-automated design optimization methodologies, various objectives are optimized simultaneously mainly based on package configurations (dimensions), material properties, and operating conditions. In the third group, optimal placement of heat generating components is performed automatically based on multiple requirements. In recent years, methodologies using (1) detailed numerical analysis models directly connected to optimization algorithms, (2) design of experiments (DoE), and (3) artificial neural networks (ANNs) have been proposed as new trends in this field. These methodologies have led to significant improvement in design optimization capabilities, while they require intensive computational effort. Advantages as well as disadvantages of these methods are discussed.
Journal of Electronic Packaging | 2005
Hamid Hadim; Tohru Suwa
A systematic multidisciplinary electronics packaging design and optimization methodology, which takes into account the complexity of multiple design trade-offs, operated in conjunction with the artificial neural networks (ANNs) technique is presented. To demonstrate its capability, this method is applied to a plastic ball grid array package design. Multidisciplinary criteria including thermal, structural, electromagnetic leakage, and cost are optimized simultaneously using key design parameters as variables. A simplified routability criterion is also considered as a constraint. ANNs are used for thermal and structural performance predictions which resulted in large reduction in computational time. The present methodology is able to provide the designers a tool for systematic evaluation of the design trade-offs which are represented in the objective function. This methodology can be applied to any electronic product design at any packaging level from the system level to the chip level.
Microelectronics Journal | 2008
Tohru Suwa; Hamid Hadim
A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5^oC, compared to the case in which only the wiring length is minimized.
International Journal of Numerical Methods for Heat & Fluid Flow | 1999
G. Chen; Hamid Hadim
The objective of the present work was to perform a detailed numerical study of laminar forced convection in a three‐dimensional square duct packed with an isotropic granular material and saturated with a Newtonian fluid. Hydrodynamic and heat transfer results are reported for three different thermal boundary conditions. The flow in the porous medium was modeled using the semi‐empirical Brinkman‐Forchheimer‐extended Darcy model which also included the effects of variable porosity and thermal dispersion. Empirical models for variable porosity and thermal dispersion were determined based on existing three‐dimensional experimental measurements. Parametric studies were then conducted to investigate the effects of particle diameter, Reynolds number, Prandtl number and thermal conductivity ratio. The results showed that channeling phenomena and thermal dispersion effects are reduced considerably in a three‐dimensional duct compared with previously reported results for a two‐dimensional channel. It was found that the Reynolds number affects mainly the velocity gradient in the flow channeling region, while the particle diameter affects the width of the flow channeling region. As the Reynolds number increases or as the particle diameter decreases (i.e., when the inertia and thermal dispersion effects are enhanced), the Nusselt number increases. The effects of varing the Prandtl number on the magnitude of the Nusselt number were found to be more significant than those of the thermal conductivity ratio. Finally, the effects of varing the duct aspect ratio on the friction factor can be neglected for small particle diameter (Dp ≤ 0.01) or for high particle Reynolds number (Red ≥ 1000) due to the dominant bulk damping resistance from the porous matrix (Darcy term) or strong inertia effects (Forchheimer term), respectively.
Nano Research | 2014
Weihe Xu; Evgeny Nazaretski; Ming Lu; Hamid Hadim; Yong Shi
AbstractThermoelectric oxide nanofibers prepared by electrospinning are expected to have reduced thermal conductivity when compared to bulk samples. Measurements of nanofibers’ thermal conductivity is challenging since it involves sophisticated sample preparation methods. In this work, we present a novel method suitable for measurements of thermal conductivity of a single nanofiber. A microelectro-mechanical (MEMS) device has been designed and fabricated to perform thermal conductivity measurements on a single nanofiber. A special Si template was designed to collect and transfer individual nanofibers onto a MEMS device. Pt was deposited by a focused ion beam to reduce the effective length of a prepared nanofiber. La0.95Sr0.05CoO3 nanofibers with diameters of 140 nm and 290 nm were studied and characterized using this approach at room temperature. Measured thermal conductivities yielded values of 0.7 W·m−1·K−1 and 2.1 W·m−1·K−1, respectively. Our measurements in La0.95Sr0.05CoO3 nanofibers confirmed that a decrease of linear dimensions has a profound effect on its thermal conductivity.
9th AIAA/ASME Joint Thermophysics and Heat Transfer Conference Proceedings | 2006
Tohru Suwa; Hamid Hadim
*† A multidisciplinary optimization methodology for placement o f heat generating cells on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology, which is based on a combination of a superposition method and artificial neural networks (ANNs) is developed for this study. Radial bases function network is trained using finite element models and are integrated to predict the temperature distribution on a silico n chip due to a single heat generating transistor in a cell. A superposition method is used to calculate the temperature distribution on a silicon chip due to multiple heat generating transistors. Using the artificial neural networks, the predicted tempera ture distribution in the silicon chip is obtained in a much shorter time than with a full finite element model and with comparable accuracy. The main advantage of the present multi -disciplinary design and optimization methodology is its ability to handle m ultiple design objectives simultaneously for optimized placement of heat generating cells. This unique capability distinguishes the present methodology from existing ones. To demonstrate its capabilities, the present methodology is applied to a test case involving placement optimization of multiple heat generating cells on a silicon chip. The results indicate that a substantial reduction in maximum junction temperature combined with optimized wiring length can be obtained. The placement optimization results indicate that block placement rather than cell placement improves the maximum temperature in a silicon chip.