Hamid Mehrvarz

A novel multi-input floating-gate MOS four-quadrant analog multiplier

A novel four-quadrant analog multiplier using multi-input floating-gate MOS (MFMOS) transistors has been designed and fabricated using a 2-/spl mu/m double-poly double-metal P-well CMOS process. It is essentially based on the quarter-square technique which relies on the square-law characteristic of the MOS transistor in the saturation region. The multiplier is realized with only four MFMOS transistors and a current source. The input range is 100% of the supply voltage and accepts either differential, single-ended, or floating input signals. Measured nonlinearity and total harmonic distortion are 0.2% and 0.5%, respectively, under full scale input conditions. Input noise is 170 /spl mu/V (rms), giving a 95 dB input dynamic range. The power dissipation is 1.1 mW and bandwidth is 12 MHz. Second-order effects on the multiplier performance have also been analyzed.

Ideal GaP/Si heterostructures grown by MOCVD: III-V/active-Si subcells, multijuntions, and MBE-to-MOCVD III-V/Si interface science

High-quality, heterovalent nucleation of defect-free epitaxial GaP on (100)-oriented Si substrates is an enabling accomplishment toward a pathway for the creation of III-V/Si multijunction photovoltaic devices in which the Si growth substrate can simultaneously act as a near-ideal sub-cell through a monolithic metamorphic GaInP/GaAsP/Si structure. While recent efforts have achieved this goal via molecular beam epitaxy (MBE), the science developed in those efforts is fundamental to the GaP/Si interface. Here this knowledge is utilized to achieve the successful transition from MBE to an all-MOCVD (metal-organic chemical vapor deposition) process, in which all nucleation-related defects are simultaneously and totally avoided for ideal GaP/Si interfaces and subsequent metamorphic III-V materials. Four main topics are presented: (1) GaP/Si(100) grown by MOCVD free of antiphase domains and stacking defects; (2) growth, fabrication, and testing of GaP/active-Si sub-cells; (3) MOCVD/MBE-grown GaAsP/active-Si multijunction structures and component cells having target lattice constants and bandgaps for high efficiency dual and triple junction cells, and (4) comparative interface studies of MBE- and MOCVD-grown III-V/GaP/Si cell architectures.

A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs

A pseudologarithmic rectifier using multi-input floating-gate MOS (MFMOS) transistors is presented in this paper. The rectifiers consist of unbalanced bias matched MFMOS transistor differential pairs. The transfer characteristics of each subrectifier are determined by an appropriate choice of transistor aspect ratio and capacitive input coupling ratio such that in the summation of the output currents from each rectifier stage, the overall transfer characteristics closely approximates that of a true logarithmic behavior. It is operable at low supply voltage (/spl plusmn/0.9 V) and has low temperature dependence. Measured dynamic range of 27 dB and 16.5 dB, with a corresponding logarithmic error of /spl plusmn/0.7 dB and /spl plusmn/0.35 dB, has been obtained for three-stage and two-stage pseudologarithmic rectifiers, respectively, at room temperature. The measured logarithmic error for the three-stage pseudologarithmic rectifier at 125/spl deg/C is /spl plusmn/1.05 dB which is an increase of /spl plusmn/0.35 dB over a 100/spl deg/C range.

Designing Bottom Silicon Solar Cells for Multijunction Devices

We report on efforts to design high-efficiency silicon homojunction subcells for use in multijunction stack devices. Both simulation and experimental works have been performed looking at a silicon solar cell under a truncated spectrum below 1.5 eV filtered by the upper layers in the multijunction stack. Good agreement is seen between the modeling and experimental results, identifying different emitter design requirements when the solar cell operates under a full or truncated spectrum. A well-passivated front surface, i.e., with low-interface surface recombination velocity, required a lightly doped emitter profile to maximize open-circuit voltage (Voc), while a high-interface recombination surface requires a heavily doped for higher Voc values. The impact on short-circuit current density (Jsc) is found to be minimal, even with large variations in the interface recombination and emitter profiles. In a tandem stack, an interface with low- and high-interface recombination velocities would require lightly doped and intermediate-doped emitters, respectively, for maximum conversion efficiency (η).

Low Voltage and Mismatch Analysis of Quadruple Source Coupled Multi-input Floating-gate Mosfet Multiplier with Offset Trimming

Considerations for optimisation of the MFMOS(Multi-input Floating-gateMosfet) multiplier for gain, minimal total harmonic distortion, low supplyvoltage operation and offset trimming are considered in this paper. Analysis shows that good matching between pairs of devices are essential forlow harmonic distortion. Results from simulation studies show that offsettrimming can be facilitated by connecting the dc bias inputs in pairs andbiasing them separately. A ±1.5 volt supply MFMOS multiplier has been designed and fabricated. Measured THD and nonlinearity at fullscale input are 0.8% and 0.5%, respectively. Bandwidth is more than 20 MHz and input dynamic range over a 0-1 MHz bandwidth is92.6 db. The lowest measured operable supply voltage is w±0.9 volt.

Design of bottom silicon solar cell for multijunction devices

We report on efforts to design high efficiency silicon sub-cells for use in multijunction stack devices. Both simulation and experimental work have been performed looking at a silicon solar cell under a truncated spectrum due to the optical filtering of the upper layers in the multijunction stack. The truncation for our case occurs for photon energies above 1.5 e V. Good agreement is seen between the modeling and experiments, with very different design features being identified, as compared to the design for a high efficiency solar cell under a full spectrum. When a well passivated front surface is achieved i.e. low interface recombination velocity, we see that a lightly-doped emitter profile maximizes the open circuit voltage (Voc). When a high interface recombination is present, however, heavily-doped profiles exhibit the higher Voc values. The impact on short circuit current (Jsc) is seen to be minimal even with large variations in the interface recombination and emitter profiles.

Large area efficient interface layer free monolithic perovskite/homo-junction-silicon tandem solar cell with over 20% efficiency

Monolithic perovskite/silicon tandem solar cells show great promise for further efficiency enhancement for current silicon photovoltaic technology. In general, an interface (tunnelling or recombination) layer is usually required for electrical contact between the top and the bottom cells, which incurs higher fabrication costs and parasitic absorption. Most of the monolithic perovskite/Si tandem cells demonstrated use a hetero-junction silicon (Si) solar cell as the bottom cell, on small areas only. This work is the first to successfully integrate a low temperature processed (≤150 °C) planar CH3NH3PbI3 perovskite solar cell on a homo-junction silicon solar cell to achieve a monolithic tandem without the use of an additional interface layer on large areas (4 and 16 cm2). Solution processed SnO2 has been effective in providing dual functions in the monolithic tandem, serving as an ETL for the perovskite cell and as a recombination contact with the n-type silicon homo-junction solar cell that has a boron doped p-type (p++) front emitter. The SnO2/p++ Si interface is characterised in this work and the dominant transport mechanism is simulated using Sentaurus technology computer-aided design (TCAD) modelling. The champion device on 4 cm2 achieves a power conversion efficiency (PCE) of 21.0% under reverse-scanning with a VOC of 1.68 V, a JSC of 16.1 mA cm−2 and a high FF of 78% yielding a steady-state efficiency of 20.5%. As our monolithic tandem device does not rely on the SnO2 for lateral conduction, which is managed by the p++ emitter, up scaling to large areas becomes relatively straightforward. On a large area of 16 cm2, a reverse scan PCE of 17.6% and a steady-state PCE of 17.1% are achieved. To our knowledge, these are the most efficient perovskite/homo-junction-silicon tandem solar cells that are larger than 1 cm2. Most importantly, our results demonstrate for the first time that monolithic perovskite/silicon tandem solar cells can be achieved with excellent performance without the need for an additional interface layer. This work is relevant to the commercialisation of efficient large-area perovskite/homo-junction silicon tandem solar cells.

Empirical and Quokka simulated evidence for enhanced V OC due to limited junction area for high efficiency silicon solar cells

A new design for high efficiency silicon solar cells with the use of limited p-n junction area and point Al rear contact is proposed. In this work, planar test devices with different emitter area and spacing are fabricated to demonstrate the limited junction area (LIA) design can improve VOC for a well-designed cell structure. Interim lifetime and PL measurements during fabrication confirm lower dark saturation current (I0) and higher implied VOC (iVOC) in the LIA samples with a robust surface passivation scheme. Higher VOC and efficiency are also simulated with Quokka on some LIA devices compared to the full area emitter control sample.

The effect of rear surface passivation layer thickness on high efficiency solar cells with planar and scattering metal reflectors

Rear surface reflector of solar cell is designed to improve light collection capacity by allowing the low energy photons to go through multiple bounces inside the solar device before escaping. In this paper, we investigate the thickness effect of rear SiO2 surface passivation layer on both optical and electrical properties of front-planar high efficiency PERT (Passivated Emitter and Rear Totally-Diffused) solar cells. Two kinds of metal reflectors are fabricated: the conventional planar reflectors by evaporated Al and the novel scattering reflectors by self assembled Ag nanoparticles. We find that the thickness dependence of rear SiO2 layer (from 8 nm - 134 nm) on photocurrent shows an asymmetry for planar and scattering reflectors, moreover, the scattering reflectors perform much better than the planar reflectors under all tested SiO2 thicknesses. A maximum current enhancement (calculated from wavelength 900 nm to 1200 nm) of 12.1% is presented for planar reflector with 134 nm SiO2 film, and 18.4% for scattering reflector with the optimized 19 nm rear SiO2 film. Additionally, by adding a detached metal mirror, the maximum current enhancement from scattering reflector jumps to 27.0%. Effective optical path length Z is calculated to study the light trapping (optical properties) under various SiO2 thicknesses for both reflectors. Diffusion length L is calculated to track the electrical performance. It is shown that thicker SiO2 is of benefit for both optical and electrical properties when planar Al reflector is used. However, for scattering reflectors, thinner SiO2 is preferable for optical enhancement, but thicker SiO2 is desirable for electrical gain. 19 nm SiO2 is found to be the best choice for cells with scattering reflectors, considering both effects.

A “smart stack” triple-junction cell consisting of InGaP/GaAs and crystalline Si

Smart stack is a handy method to construct multi-junction tandem through the interconnection of different types of solar cells using a Pd nanoparticle array as a bonding mediator. In this study, a triple-junction cell was fabricated from InGaP/GaAs and crystalline Si subcells using the smart stack method, which resulted in a conversion efficiency of 23.2%. The EQE analysis of the smart stack cell was also carried out, suggesting that higher efficiencies are feasible through better current matching among the subcells.