Han-Han Lu

Using Ge-Doped La-Oxynitride as Interfacial Passivation Layer for GaAs Metal-Oxide-Semiconductor Capacitors

The GaAs MOS capacitors using ZrON as high-k gate dielectric with LaGeON or LaON as an interfacial passivation layer (IPL) are fabricated and their electrical and interfacial properties are investigated. Compared to their counterpart without IPL, introducing LaGeON or LaON as IPL results in a large improvement of interface quality and electrical properties of the GaAs MOS devices, for example, improved capacitance-voltage behavior, reduced interface-state density and gate leakage current, and enhanced device reliability. Moreover, because of Ge incorporation, the LaGeON IPL becomes more stable and can more efficiently block the Ga/As out-diffusion and O in-diffusion to reduce the defect-related Ga/As-O and As-As bonds at the GaAs surface, thus exhibiting the best interface quality and electrical properties, and high device reliability.

Plasma-Nitrided Ga 2 O 3 (Gd 2 O 3 ) as Interfacial Passivation Layer for InGaAs Metal–Oxide– Semiconductor Capacitor With HfTiON Gate Dielectric

Plasma nitridation is used for nitrogen incorporation in Ga₂O₃(Gd₂O₃) (GGO) as interfacial passivation layer for an InGaAs metal-oxide-semiconductor capacitor with a HfTiON gate dielectric. The nitrided GGO (GGON) on InGaAs can improve the interface quality with a low interface-state density at midgap (1.0 × 10¹² cm^-2 eV^-1), and result in good electrical properties for the device, e.g., low gate leakage current (8.5 × 10^-6 A/cm² at V_g = 1 V), small capacitance equivalent thickness (1.60 nm), and large equivalent dielectric constant (24.9). The mechanisms involved lie in the fact that the GGON interlayer can effectively suppress the formation of the interfacial In/Ga/As oxides and remove excess As atoms on the InGaAs surface, thus unpinning the Femi level at the GGON/InGaAs interface and improving the interface quality and electrical properties of the device.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm−2 eV−1 at midgap), smaller gate leakage current (9.5 × 10−5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

Influences of Remote Coulomb and Interface-Roughness Scatterings on Electron Mobility of InGaAs n MOSFET With High- k Stacked Gate Dielectric

A physics-based electron-mobility model including remote Coulomb scattering by fixed charge in high-k dielectric and remote interface-roughness scattering originated from the fluctuation of high-k /interlayer interface is established for InGaAs MOSFET, and the validity of the model is confirmed by good agreement between simulated results and experimental data. Effects of structural and physical parameters of the devices on the electron mobility are analyzed using the model, and the results show that smoother high-k /interlayer interface, reasonably high permittivities for the interlayer and high-k dielectric, and less fixed charge in the high-k dielectric are desired to enhance the electron mobility and simultaneously keep further scaling of equivalent oxide thickness.

An equivalent capacitance model of oxide traps on frequency dispersion of C-V curve for MOS devices

An equivalent capacitance model is developed to explain frequency dispersion in accumulation or near-flatband region of C-V curve for MOS devices. This model is based on Fermi-Dirac statistics and tunneling mechanism of carriers and is simpler and more intuitive than the previous lumped-circuit model due to considering only capacitance of oxide traps. Using different space distribution of the oxide traps, the validity of the model is confirmed by fitting to experimental data of MOS devices with different types of substrates and channel concentrations.

Improved interfacial properties of GaAs MOS capacitor with NH3-plasma-treated ZnON as interfacial passivation layer

The GaAs MOS capacitor was fabricated with HfTiON as high- k gate dielectric and NH 3 -plasma-treated ZnON as interfacial passivation layer (IPL), and its interfacial and electrical properties are investigated compared to its counterparts with ZnON IPL but no NH 3 -plasma treatment and without ZnON IPL and no plasma treatment. Experimental results show that low interface-state density near midgap (1.17×10 12 cm -2 eV -1 ) and small gate leakage current density have been achieved for the GaAs MOS device with the stacked gate dielectric of HfTiON/ZnON plus NH 3 -plasma treatment. These improvements could be ascribed to the fact that the ZnON IPL can effectively block in-diffusion of oxygen atoms and out-diffusion of Ga and As atoms, and the NH 3 -plasma treatment can provide not only N atoms but also H atoms and NH radicals, which is greatly beneficial to removal of defective Ga/As oxides and As-As band, giving a high-quality ZnON/GaAs interface.

Equivalent distributed capacitance model of oxide traps on frequency dispersion of C-V curve for MOS capacitors

An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C–V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi–Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive.