Han Ke

Verification of AMBA Bus Model Using SystemVerilog

A verification environment to verify an ARM-based SoC (system-on-chip) by using system Verilog is presented in this paper. The new verification constructs can be easily reused for the objected-oriented feature of SystemVerilog. The paper also introduced how to design the AMBA (advanced microprocessors bus architecture) verification IP (intellectual property) by SystemVerilog, which include AHB (advanced high performance bus) master and AHB monitor. The verification IP can be reused to verify any AMBA protocol based SoC. To reduce the time spending in the verification, a reference model designing method is also discussed in the paper.

A Testable Design Method for Memories by Boundary Scan Technique

This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC). A is designed to test the embedded Flash. The feature of the Flash TAP (Test Access Port) complies with the IEEE std.1149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test) circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.