Han-Shin Youn

A Digitally Controlled Critical Mode Boost Power Factor Corrector With Optimized Additional On Time and Reduced Circulating Losses

In many low-to-mid power applications, critical mode boost power factor corrector converters are widely used because of its low switching loss and simple control. However, near the zero crossing of the input line voltage, an input current distortion and a low power factor are caused by delayed switching period and negative input currents. Generally, an additional on-time method according to the input voltage is used to compensate the input current distortion. However, a detailed quantitative analysis for the exact additional on time has not been studied till now. In this paper, the explicit form of the optimized additional on time has been obtained using a quantitative analysis and the advantage of the digital control. From a state trajectory and “net input charge” analysis, it is shown that the optimized on time should be related to not only the input voltage, but also the output power. Also, in order to improve the efficiency in a high input and light load condition, circulating currents are reduced in the inevitable dead angle with a gate turning-off technique. By using digital control, the optimized additional on time and the gate turn-off technique have been implemented with the 90-230 Vrms input and 380 V/200 W output prototype.

Integrated Asymmetrical Half-Bridge Zeta (AHBZ) Converter for DC/DC Stage of LED Driver With Wide Output Voltage Range and Low Output Current

The conventional half-bridge converter for a dc/dc stage in wide-output-voltage and constant-output-current applications such as LED drivers is limited in achieving high efficiency because it is difficult to be designed optimally. To overcome this limitation, an integrated asymmetrical half-bridge zeta converter is proposed for high efficiency in the overall output voltage range. The proposed converter can be simply implemented by replacing a snubber diode with a switch. The proposed converter operates similar to the asymmetrical half-bridge converter by turning off the switch in the low-output-voltage region, which enables it to have a small dc-offset current in the transformer. In the high-output-voltage region, the proposed converter operates similar to the half-bridge zeta converter by turning on the switch, which has small transformer core loss. Therefore, the proposed converter can achieve high efficiency over the entire output voltage range compared with the conventional converters. The validity of the proposed converter is confirmed by experimental results from a prototype with 400-V input and 90-180-W/3-A output.

A Digital Predictive Peak Current Control for Power Factor Correction With Low-Input Current Distortion

A digital predictive peak current control (PPCC) employing the adaptive slope compensation is proposed in this paper. The PPCC precisely predicts the peak current reference with the adaptive slope compensation according to operation regions and load conditions. Thereby, the PPCC can control the peak inductor current, and it significantly reduces the total harmonic distortion compared to that of the conventional digital average current control with duty ratio feed-forward which is widely used. In addition, parts of the PPCC are implemented by utilizing the internal high-resolution ramp generator and comparator of a digital signal processor without external components. The principle and analysis of the PPCC are presented, and the performance and feasibility are verified by experimental results with universal input (90 Vrms ~ 260 Vrms) and 750 W - 400 V output laboratory prototype.

A Digital Phase Leading Filter Current Compensation (PLFCC) Technique for CCM Boost PFC Converter to Improve PF in High Line Voltage and Light Load Conditions

This paper proposes a digital phase leading filter current compensation (PLFCC) technique for a continuous conduction mode boost power factor correction to improve PF in high line voltage and light load conditions. The proposed technique provides a corrected average inductor current reference and utilizes an enhanced duty ratio feed-forward technique which can cancel the adverse effect of the phase leading currents caused by filter capacitors. Moreover, the proposed PLFCC technique also provides the switching dead-zone in nature so the switching loss can be reduced. Therefore, the proposed PLFCC can significantly improve power quality and can achieve a high efficiency in high line voltage and light load conditions. The principle and analysis of the proposed PLFCC are presented, and performance and feasibility are verified by experimental results from the universal input (90-260 VAC) and 750 W-400 V output laboratory prototype.

A simple control scheme for improving light-load efficiency in a full-bridge LLC resonant converter

In this paper, a load adaptive phase-shift control is proposed for the full-bridge LLC resonant converter to improve light-load efficiency. The proposed method reduces the effective duty ratio and the magnetizing current. Therefore, the core loss on transformer and the turn-off switching loss on switches are significantly reduced. To confirm the validity of this study, the prototype with 320~400V DC input, 12V/40A DC output is experimented.

A high efficiency critical mode boost PFC using a variable inductor

In low-to-mid power applications, a critical conduction mode (CRM) boost power factor corrector (PFC) is widely used due to its simple control and a reduced switching loss. One of the important characteristics of CRM boost PFC is that the switching frequency is not constant and the range of variation is wide. Due to this variability of the switching frequency, there is a design guideline, which must be satisfied. That is, the minimum switching frequency must be higher than the audible frequency. In that reason, a small boost inductance is required to increase the switching frequency. However, this increases the switching loss resulting in a reduced efficiency. In this paper, a new method of improving the efficiency using a variable inductor is proposed. A variable inductor can be implemented by a simple auxiliary circuit. At nominal, where a high efficiency is required, the proposed method operates with a large inductance, which results in the improved efficiency with a decreased switching frequency. On the other hand, when the switching frequency decreases to the audible frequency, the inductance is changed to a smaller value, keeping the frequency higher than the audible frequency over all the range of input line voltage.

Zero-voltage-switching interleaved two-switch forward converter with phase-shift control

In this paper, a zero-voltage switching (ZVS) interleaved two-switch forward (ITSF) converter employing a phase-shift control is proposed. Since the proposed converter is based on a two-switch forward (TSF) topology, it has no chance to be a short circuit causing device failure. Furthermore, the interleaving operation of two TSF converters reduces the output filter size. In addition, by applying the phase-shift control on the common clamping diode structure at the primary side, all primary switches can be turned on under ZVS conditions. The operational principle, theoretical analysis, and design consideration are presented. To confirm the performance of the proposed circuit, experimental results from a 480 W, 100 kHz, and 400 V to 48 V prototype are presented.

A high efficiency half-bridge LLC converter with simple hold-up compensation circuit

The half-bridge (HB) LLC converter has been widely used in medium power applications because of low component count, no transformer dc-offset current, and wide zero-voltage-switching (ZVS) range. However, the HB LLC converter should be designed with small transformer magnetizing inductance to obtain high voltage gain in wide-input-voltage applications with the hold-up time conditions. It causes the HB LLC converter to have large conduction and switch turn-off losses in the primary side at nominal input where a high efficiency is required. To overcome these problems, a simple control method of the HB LLC converter with one additional switch and capacitor in the primary side is proposed in this letter. At nominal input, since the proposed method enables the HB LLC converter to operate with large transformer magnetizing inductance, it can reduce the conduction and switch turn-off losses in the primary side, which makes a high efficiency. On the other hand, during the hold-up time, since the proposed method increases the resonant capacitance by turning on one additional switch, the HB LLC converter can obtain high voltage gain. To confirm the validity of the HB LLC converter with the proposed method, a 325-385V input and 56V/350W output laboratory prototype is built and tested.

A New Center-Tapped Half-Bridge Zeta Converter With Small Transformer DC-Offset Current and Low Voltage Stress

In this paper, an asymmetrical half-bridge (AHB) converter employing a new center-tapped zeta rectifier (CTZR) is proposed to achieve a high efficiency in wide-input-voltage and low-output-current applications. Due to the proposed CTZR with high dc conversion ratio and extended maximum duty cycle above 0.5, the transformer turns ratio of the proposed converter can be increased, which decreases the transformer dc-offset current compared with that of the AHB converter. Therefore, its transformer core size is decreased. Moreover, it has a wide zero-voltage-switching range with small transformer leakage inductor, which improves light and medium load efficiency. Furthermore, since it has low voltage stress on the secondary diode, its conduction loss can be reduced. In addition, due to the elimination of a diode, the snubber loss in the secondary side is reduced compared with the AHB converter. Therefore, the proposed converter can achieve a higher efficiency compared with the AHB converter without additional devices. To confirm the operation, features, and validity of the proposed converter, a 250-400 V input and 50 V/250 W output laboratory prototype is built and tested.

A new efficient hold-up time compensation method for high efficiency DC/DC stage

The conventional two-stage structured power-supply units (PSUs) requiring the hold-up time operation have generally low efficiency dc/dc stage because it is difficult to be designed optimally. As a result, to improve the efficiency of the dc/dc stage, many hold-up time compensation methods have been presented. However, they cannot still optimize the dc/dc stage due to its bad influence on the design conditions. In addition, they can only be employed in certain dc/dc topologies as well as they still ill-affect the design conditions of the dc/dc stage. Therefore, in this paper, a new hold-up time compensation method is proposed to overcome the conventional limitation. Compared to the conventional method, since the proposed method delivers the output power by using not the dc/dc stage but the power factor correction (PFC) stage during the hold-up time, it can optimize the dc/dc stage at the nominal state without any bad influence, which enables the dc/dc stage achieve a high efficiency. Furthermore, it can be widely applied to various dc/dc stages. The validity of the proposed method is confirmed by experimental results from a prototype with 90-264Vrms input and 480W/10A output.