Handy Fortin Blanchette

An Efficient DSP-FPGA-Based Real-Time Implementation Method of SVM Algorithms for an Indirect Matrix Converter

This paper proposes a real-time DSP- and FPGA-based implementation method of a space vector modulation (SVM) algorithm for an indirect matrix converter (IMC). Therefore, low-cost and compact control platform is built using a 32-bit fixed-point DSP (TMS320F2812) operating at 150 MHz and a SPARTAN 3E FPGA operating at 50 MHz. The method consists in using the event-manager modules of the DSP to build specified pulses at its PWM output peripherals, which are fed to the digital input ports of a FPGA. Moreover, a simple logical processing and delay times are thereafter implemented in the FPGA so as to synthesize the suitable gate pulse patterns for the semiconductor-controlled devices. It is shown that the proposed implementation method enables high switching frequency operation with high pulse resolution as well as a negligible propagation time for the generation of the gating pulses. Experimental results from an IMC prototype confirm the practical feasibility of the proposed technique.

A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters

A comprehensive approach to the real-time simulation of power converters using a state-space representation is covered in this paper. Systematic formulations of state-space equations as well as a new switch model are presented. The proposed switch model exhibits a natural switching behavior, which is a valuable characteristic for the real-time simulation of power converters, thereby allowing individual treatment of switching devices irrespective of the converter topology. Successful implementations of the proposed switch model on a field programmable gate array (FPGA) device are reported, with two alternative approaches: 1) precomputing network equations for all switch state combinations and 2) solving network equations on-chip using the Gauss-Seidel iterative method. A two-level three-phase voltage source converter is implemented using the first approach, with a time step of 80 ns and a switching frequency of 200 kHz. Ideal and nonideal boost converters are also implemented on FPGA using the second approach, with a time step of 75 ns and a switching frequency of 20 kHz. Comparison with SPICE models shows that the proposed switch model offers very satisfactory accuracy and precision.

Very-high speed control of an FPGA-based finite-element-analysis permanent magnet synchronous virtual motor drive system

Presented in this paper are the results of tests involving high-speed closed-loop control of a virtual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) card, connected to an external controller. Three types of motor drive models are actually implemented on the FPGA card of the RT-LAB based real-time simulator used: a Park (d-q) model along with two different implementations of finite element analysis (FEA) based models. The first FEA model, previously published, is an FPGA implementation of a FEA model with an inductance calculation routine running on an associated CPU of the real-time simulator. The second FEA model has its inductance routine coded in the FPGA. One of the main objectives of the paper will be to compare the performance of the two FEA models. By virtue of the faster, FPGA-located, inductance routine update rate of the new model, it is expected that its precision at very high speed will be greater than the previous model, which was shown to be limited to 400 Hz electric frequency.

A new five-level buck-boost active rectifier

In this paper a new single-phase five-level buck-boost active rectifier is introduced called capacitor tied switches (CTS). The proposed rectifier has two independent DC outputs that can be connected to two different loads. Different switching states and the average mode of the proposed topology are analyzed to design the associated controller aims at regulating the two output DC voltages, generating five-level voltage at the input of the rectifier and finally draw unity power factor and sinusoidal current from AC grid. From AC grid view, the rectifier works in boost mode however the generated DC voltage can be split into two separate outputs which may be less than the AC peak voltage or even more leads to work in both buck and boost operation mode. Full simulation results are shown and analyzed to validate the effective operation and good dynamic performance of the proposed five-level buck-boost rectifier.

A survey on modeling, control, and dc-fault protection of modular multilevel converters for HVDC systems

The modular multilevel converter (MMC) is becoming one of the most promising topology in multilevel converter series especially for high-voltage and high-power applications. This valuable features, nominates MMCs to interface high-voltage and high-power renewable energy resources into modern HVDC electric grids for more penetration of renewable energy. This paper investigates recent modelling, control, and dc-fault protection techniques that have been applied to MMCs.

Switching time model updating for the real-time Simulation of power-electronic circuits and motor drives

The main hurdle in achieving real-time performance for the simulation of power-electronic circuits is the large calculation effort required to update the model after a discontinuous change in switch impedance. The method presented here suggests that by separating the switch model from the rest of the circuit, only a much smaller equation set needs updating. Thus, it reduces the update effort to a level where it is no longer the bottleneck of the overall simulation loop. Unlike previous works on this issue, the method is independent on both the simulation approach and the circuit topology. The method has been tested on a variety of circuits with impressive results, two of which are presented here. First, there is a complete HVdc system, representing the higher limit in size and complexity. Second, a pulse-width-modulated motor drive with an external controller in a hardware-in-the-loop configuration represents a higher limit in performance requirements. Both test circuits are simulated in real time on a low-cost off-the-shelf personal computer, using the xPC technology from Simulink and automatic generation of optimized code, and are compared to a very precise variable step offline simulation.

Influence of High-Frequency Near-Field Coupling Between Magnetic Components on EMI Filter Design

This work presents a detailed analysis of magnetic component coupling and its influence on EMI filter design. In contrast with other literature, the novelty of this paper reveals that magnetic coupling should be divided into two categories: low-frequency coupling and high-frequency coupling. It is proven that coupling is frequency related and high-frequency near-field stray flux distribution can be differ dramatically from low frequency condition. The change of the near-field stray flux distribution is caused by displacement current from stray capacitors. By using the Biot-Savart equation, high-frequency near-field distribution can be well predicted and matched with experimental results. In addition, single stage DM LC filters are utilized to demonstrate the influence of high-frequency coupling.

A new 7L-PUC multi-cells modular multilevel converter for AC-AC and AC-DC applications

In this paper, a new cell based Modular Multilevel Converter (MMC) for AC-AC and AC-DC applications is presented. The new topology makes use of an efficient Packed U-Cells (PUC) structure to form the Multi-Cells Modular Multilevel Converters (M3C). It is a member of MMC root family, with extended operational capability covering therefore AC-AC and AC-DC modes of operation. A dynamic model of the PUC and the single phase M3C will be used along with predictive control method to validate the effectiveness of different operation modes of the converter.

Indirect Matrix Converters' Enhanced Commutation Method

This paper introduces an enhanced commutation method applied to the indirect matrix converter topology. It is based on the detection of the load current polarity so as to cancel the turn-on delay times of the load-side converters switches. The proposed method allows the grid-side converter devices to commutate at zero current with larger time interval widths provided for this safe commutation. Moreover, it has been shown through experimental results, carried out on a laboratory prototype of the matrix converter, that a substantial improvement of line current total harmonic distortion is achieved.

A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1