Hannu Luoto

Silicon-on-Insulator Wafers with Buried Cavities

Direct bonding and mechanical thinning of pre-etched silicon wafers have been studied for the fabrication of silicon-on-insulator (SOI) wafers with buried cavities. The thin Si diaphragm over the cavity is deflected downward during the grinding and polishing, as the thinning is carried out without supporting the diaphragm. The deflection causes thickness variation for the Si diaphragm that can also be observed as a hill on the wafer surface after thinning. The results show that the thickness variation of the Si diaphragm increases with increasing cavity size and with decreasing SOI layer thickness. After grinding the measured hill height was about 1.5 μm for a 20-μm-thick Si diaphragm over a 1 X 1 mm cavity. The hill height was reduced to less than 0.5 μm when a small supporting column was placed under the diaphragm. With polishing the hill height was further reduced to <0.1 μm. It appears that mechanical thinning of the bonded wafers with pre-etched cavities is a viable method for various applications.

Transfer of thin Si layers by cold and thermal ion cutting

We have used the crack-opening method to study the mechanical exfoliation behavior in hydrogen-implanted and bonded Cz Si. We found that the crystal orientation and boron doping influence the temperature required for mechanical layer transfer. Boron implantation at doses >1013 cm−2 reduces the annealing temperature needed for mechanical exfoliation. The boron-doped epilayers followed similar exfoliation behavior as the boron-implanted samples. No lowering of the exfoliation temperature was observed for compensated and arsenic-doped Si layers. The hydrogen implantation converted the silicon wafer surface from p-type to n-type. The as-transferred Si layer was also found to be n-type after annealing at 200–450 °C. The p-type conductivity was restored upon annealing at around 600 °C. We believe that this conductivity conversion is due to the combined effect of ion-enhanced thermal donors and the presence of H-related shallow donors in the implanted layer. The p-type conductivity is restored at higher temperatures following the dissociation of the thermal donors and the out-diffusion of hydrogen. We also report that a good-quality silicon on glass layer can be obtained by the bonding and ion-cutting processes.

Through-Wafer Polysilicon Interconnect Fabrication with In-Situ Boron Doping

Bulk micromachining technology can be used to produce conducting through-wafer polysilicon interconnects, i.e., polysilicon via plugs. This paper presents the process fabrication steps of polysilicon via plugs with in-situ boron doped polysilicon material in order to develop fast one-step doping process, without additional diffusion. The via holes can be processed by high-aspect ratio silicon etching with inductively coupled plasma (ICP). Only one deep ICP etching is required if the wafer is mechanically ground (from the backside) to reduce the wafer thickness of 500 microns to a typical of 400, in order to overcome deep etching sidewall profile problems. After hole formation with ICP the via plug fabrication process continues by growing an insulating thermal oxide layer with a thickness of the order of a micron, followed by an in-situ boron doped LPCVD polysilicon growth to fill the holes with sufficient step coverage. The polysilicon growth temperature at 680°C ensures sufficient step coverage, reasonable furnace process time and enables planarization processing, such as grinding and chemical-mechanical polishing (CMP). The subsequent planar processing typically requires planarization of the polysilicon layer down to the original silicon (or oxide) surface with CMP, and some doping activation step, which usually can be performed together with some additional oxidation step. Applications of the via plugs in the field of silicon-based sensors or actuators enable significant reduction of the front surface wiring density, which opens additional space for denser packing or other desired components.

Advances in the CMP Process on Fixed Abrasive Pads for the Polishing of SOISubstrates with High Degree of Flatness

The new approach using Fixed Abrasive (FA) pads for polishing thick film Silicon-onInsulator (SOI) wafers after bonding and grinding process [1] has been further developed. The aim is a practicable industrial manufacturing process, where the major specifications especially in long term stability and removal rate should be achieved. In base line studies a stable removal rate on suitable level has been reached, while the degeneration of the total thickness variation (TTV) was limited to a clearly smaller value than that being typical for the standard stock removal polishing. The overall removal in these tests was adjusted to 2-3 µm, which removes all sub surface damage (SSD) from wafers ground by ultra fine grinding wheels with very small average abrasive particle size. The process has been able to remove all visible grindlines after removing less than 1.5 µm. In another test with a further developed high density FA pad, removal rates up to ~0.6 µm/min were achieved. The polished samples were further processed and characterized by capacitive thickness measurements gauges, optical surface inspection tool (“Magic mirror”), atomic force microscopy (AFM) and optical reflection measurements.

Polishing of bulk micro-machined substrates by fixed abrasive pads for smoothing and planarization of MEMS structures

In this work, an approach was made to use chemical mechanical polishing (CMP) by prototype fixed abrasive (FA) pads rather then conventional slurry based polishing for smoothing of bulk micro-machined and oxidized silicon wafers. A comparison is provided to conventional CMP, showing the minimization of edge rounding in case of FA use under the needed polishing step for sub-sequent wafer bonding. Simultaneously the achieved roughness provides a surface quality suitable for direct wafer bonding

Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates

The specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance. Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [1]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [2] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing. INTRODUCTION When making thick film SOI substrates a significant amount of mechanical treatment on wafers has to be done. Unlike in thin film SOI the device layer of the wafer has to be formed by removing most of the bonded top substrate during grinding and subsequent polishing. Grinding is used to adjust the required thickness, which can vary from 1 μm to more than 100 μm. Grinding leads to very flat wafers, however it leaves not only mechanical abrasion lines, but also introduces a several microns deep layer with crystalline defects [4, 5]. Therefore, subsequent polishing is needed to provide a smooth and defect-free device layer surface. Conventional slurry-based CMP leads to unsatisfactory results in terms of TTV, as the edge of the slightly smaller device layer is rounded under the removal of the damaged layer. As the required polishing amount is increasing, the TTV degenerates. Currently a polishing removal of 5 μm is needed for slurry-based CMP to remove all grindlines and 6 to 8μm is necessary to remove all crystalline damage from standard grinding processes [1]. W3.4.1 Mater. Res. Soc. Symp. Proc. Vol. 867