Tommi Suni

Effects of Plasma Activation on Hydrophilic Bonding of Si and SiO2

Low-temperature bonding of wafers has been studied utilizing reactive ion etching-mode plasma activation. The hydrophilic Si and thermally oxidized Si wafers were exposed to N 2 , Ar, or O 2 plasma prior to bonding in air or vacuum. After plasma treatment the wafers were cleaned in RCA-1 solution and/or deionized water. Strong bonding was achieved at 200°C with all the investigated plasma gases, if proper bonding and cleaning procedures were used. Extended RCA-I cleaning deteriorated the bond strength, but a short cleaning improved bonding. We found that the activation of the thermal oxide has a larger influence on the bond strength than the activation of the native oxide surface in Si/oxide wafer pairs. We suggest that the plasma treatment induces a highly disordered surface structure which enhances the diffusion of the water from the bonded interface. As a result of the plasma exposure the number of the surface OH groups is greatly increased enabling strong bonding at a low temperature.

Silicon-on-Insulator Wafers with Buried Cavities

Direct bonding and mechanical thinning of pre-etched silicon wafers have been studied for the fabrication of silicon-on-insulator (SOI) wafers with buried cavities. The thin Si diaphragm over the cavity is deflected downward during the grinding and polishing, as the thinning is carried out without supporting the diaphragm. The deflection causes thickness variation for the Si diaphragm that can also be observed as a hill on the wafer surface after thinning. The results show that the thickness variation of the Si diaphragm increases with increasing cavity size and with decreasing SOI layer thickness. After grinding the measured hill height was about 1.5 μm for a 20-μm-thick Si diaphragm over a 1 X 1 mm cavity. The hill height was reduced to less than 0.5 μm when a small supporting column was placed under the diaphragm. With polishing the hill height was further reduced to <0.1 μm. It appears that mechanical thinning of the bonded wafers with pre-etched cavities is a viable method for various applications.

Direct Bonding of Thick Film Polysilicon to Glass Substrates

In the fabrication of microelectromechanical system (MEMS) devices the encapsulation of sensors and actuators is often required. Moreover, polysilicon has proven to be an indispensable material in various applications in MEMS area. In this study, we have concentrated on the development of polishing processes for polysilicon and then bonding it to quartz, Pyrex, and low-alkali glass. Simultaneously, basic investigation of high-temperature direct bonding of polysilicon is initiated where Si/Si- and Si/Ox-bonding is studied. The main emphasis in material selection has been in thick atmospheric-pressure chemical vapor deposited polysilicon. Spontaneous bonding was achieved with all wafer combinations. Plasma-assisted polysilicon-to-glass bonding was found to yield void free interfaces, whereas high-temperature bonded couples showed void formation. Thus, low-temperature bonding for polysilicon has been enabled with an advanced polishing process.

Transfer of thin Si layers by cold and thermal ion cutting

We have used the crack-opening method to study the mechanical exfoliation behavior in hydrogen-implanted and bonded Cz Si. We found that the crystal orientation and boron doping influence the temperature required for mechanical layer transfer. Boron implantation at doses >1013 cm−2 reduces the annealing temperature needed for mechanical exfoliation. The boron-doped epilayers followed similar exfoliation behavior as the boron-implanted samples. No lowering of the exfoliation temperature was observed for compensated and arsenic-doped Si layers. The hydrogen implantation converted the silicon wafer surface from p-type to n-type. The as-transferred Si layer was also found to be n-type after annealing at 200–450 °C. The p-type conductivity was restored upon annealing at around 600 °C. We believe that this conductivity conversion is due to the combined effect of ion-enhanced thermal donors and the presence of H-related shallow donors in the implanted layer. The p-type conductivity is restored at higher temperatures following the dissociation of the thermal donors and the out-diffusion of hydrogen. We also report that a good-quality silicon on glass layer can be obtained by the bonding and ion-cutting processes.

Reliability Performance of Au-Sn and Cu-Sn Wafer Level SLID Bonds for MEMS

Wafer level Solid-Liquid Interdiffusion (SLID) bonding is used to encapsulate MEMS devices. The metals in SLID bonds can improve the reliability by absorbing mechanical and thermo-mechanical stresses. In this paper, the reliability of wafer level Au-Sn-(Ni) and Cu-Sn SLID bonds was systematically characterized and evaluated with shear/tensile tests, shear fatigue test, mixed flow gas (MFG) test, high temperature storage (HTS) test and thermal shock (TS) test. The failure modes and physical mechanisms were analyzed. Overall, the results demonstrated the high mechanical strength and reliability of SLID bonds. Utilizing the reliability results the design of seal bonds for MEMS encapsulation could be improved.

Analysis of microstructural evolution in SLID-bonding used for hermetic encapsulation of MEMS devices

The need for reliable hermetic sealing of electronic components has arisen along the increasing popularity of silicon based Micro Electro Mechanical Systems (MEMS). In this paper we have analyzed the formation and evolution interconnections made with Solid Liquid Interdiffusion (SLID) bonding by utilizing thermodynamic-kinetic method. The analysis of the phase transformations and consequent formation of stresses in Au-Sn system during bonding as well as the remelting temperatures of the Au-In-Sn interconnections can be carried out with the help of thermodynamic equilibrium diagrams. In addition, by combining qualitative thermodynamic calculations with qualitative kinetic considerations the evolution of interfacial microstructures between Ni contact metallization and the Au-Sn bonding alloy was predicted.

Thick-Film SOI Wafers: Preparation and Properties

This chapter reviews the methods of manufacturing bonded thick-film silicon-on-insulator (SOI) wafers used in MEMS applications and typical properties of wafers are also summarized, focusing on data from large-series production of wafers. It details the approach that relies on mechanical back-grinding and optical precision polishing for final thinning of the SOI film. A comprehensive discussion of semiconductor wafer bonding technology and applications can be found in Refs. SOI is a semiconductor structure consisting of a layer of single crystalline silicon separated from the bulk substrate by a thin layer of insulator. The SOI structure was created for the first time using silicon on sapphire. A review of SOI technologies with an emphasis on MEMS applications is also given. Bonded SOI wafers are composed of two silicon wafers bonded face-to-face with a buried oxide layer. One can choose the SOI parameters quite freely as the manufacturing process allows a wide range of independent wafer parameter values. Direct wafer bonding associated with mechanical thinning of the SOI layer is a generic technology that enables the fabrication of thick-film SOI wafers. It is perfectly adapted to the range of SOI layer thicknesses that are commonly used in MEMS applications. The selection of wafer type is based strongly on the performance versus overall cost per die and should include all aspects for consideration, a short description of the most important thin-film SOI manufacturing technologies are also given in this chapter.

Fabrication, electrical characterization and reliability study of partially electroplated tapered copper through-silicon vias

The fabrication, electrical characterization and reliability study of copper through-silicon via (TSV) is reported. All the fabrication steps needed in this process have a process temperature <; 250°C. The copper TSVs have two distinct features: tapered via profile and partial filling of the vias. Besides the single Kelvin cell TSVs, daisy chains having up to 1400 TSVs were also fabricated and characterized. The measured electrical resistance of a single Kelvin TSV was between 3-10 MÛ. Later, these partially filled TSVs were subjected to various thermal and electrical cycling tests to study their behavior under different stress conditions. Electrical resistance of these TSVs was found to be stable under these tests; however certain TSV failure were also observed. Preliminary study has shown that via etching and via-filling related defects were the main reasons behind these failures. These cost-effective TSVs were implemented in the wafer level capping of MEMS resonators.

Investigation of Si/SiO 2 bonding energy using recess test structure

Recess test structures are utilized in the investigation of the bonding energy of the plasma activated uncoated and SiO2 coated silicon wafers. The scanning acoustic microscope images are compared with the values obtained from the crack opening measurements.

Polishing of bulk micro-machined substrates by fixed abrasive pads for smoothing and planarization of MEMS structures

In this work, an approach was made to use chemical mechanical polishing (CMP) by prototype fixed abrasive (FA) pads rather then conventional slurry based polishing for smoothing of bulk micro-machined and oxidized silicon wafers. A comparison is provided to conventional CMP, showing the minimization of edge rounding in case of FA use under the needed polishing step for sub-sequent wafer bonding. Simultaneously the achieved roughness provides a surface quality suitable for direct wafer bonding