Hans Hauer

Highly integrated front-end electronics for spaceborne fluxgate sensors

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability (< 5 pT °C−1 MFA temperature, < ±0.2 nT within 250 h) are very satisfying and the linear gain drift of 60 ppm °C−1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm2 mg−1.

A 16-bit 60/spl mu/W multi-bit /spl Sigma//spl Delta/ modulator for portable ECG applications

To address the growing field of on-line, out-of-hospital health care a front-end ADC for portable electrocardiographic systems has been designed. The converter is realized as a first-order, 3-bit /spl Sigma//spl Delta/ with an oversampling ratio of 512. Performance is optimized to adhere to the standard IEC60601-2-47, which governs ambulatory ECG equipment. The single ended design achieves a dynamic range of 16 bits for signal offsets up to /spl plusmn/1.25V. Measured power consumption is 60 /spl mu/W with supplies of 2.6V analog and 2.2V digital.

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35µm CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.

A 92dB-DR 13mW /spl Delta//spl Sigma/ Modulator for Spaceborn Fluxgate Sensors

A 2-2 cascaded DeltaSigma modulator is adapted for near sensor digitization of the magnetic field measured by a fluxgate sensor. The chip contains three fluxgate channels (13mW each) and one voltage channel (10mW). The fluxgate channels achieve a DR of 92dB for field ranges greater than plusmn2,000nT with 10pT resolution. The chip operates up to 260krad of total ionizing dose. The chip uses 20mm2 in a 0.35mum CMOS process.

1.8-V second-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS technology

This paper deals with the design of a second-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS technology. The A/D converter structure combines a 1-bit approach along with a relatively high oversampling ratio in order to obtain a reasonable dynamic range. A circuit prototype, including the modulator itself, a current reference, and the clock signals generator, has been fabricated to operate with a 1.8-V supply. A measured SNDR equal to 87 dB is obtained for a clock frequency equal to 8 MHz, while the experimental performance of the /spl Sigma//spl Delta/ modulator is maintained in a frequency range higher than 16 MHz.

Current mode CMOS synthesis of a motor---control neural system

This paper presents an analog CMOS implementation of a neural network based on a spinal cord model. The network is comprised by three pairs of cells, Alpha motoneurons, Interneurons and Renshaw cells, which form the basic control motor system for a single limb movement in a human being. Neurons behaviour is described by a differential equation, which provides it with a dynamic performance. This network is useful to control limb movements based in an agonist pair of actuators, i.e. muscles for a human limb or electric motors or SMA fibers for machine applications. This structure has the advantage that allows independent control of limb position and stiffness, which makes it suitable for applications where inertial load compensation is a critical factor.

An analogue current---mode hardware design proposal for preprocessing layers in ART-based neural networks

In this paper, a mixed-signal current-mode chip is implemented using commercial 0.35-m technology. It performs the preprocessing task done by the first neurons layers in ART-based neural networks. Post layout simulations show an acceptable linearity error for such neural systems. The input signal swings from 20 to 50 μA. The circuit operates at a supply voltage of 3.3 V with 200 kHz bandwidth.

CMOS analog implementation of a simplified spinal cord neural model

This paper presents an analog CMOS implementation of a neural network based on a spinal cord model. The network is comprised by three pairs of cells, Alpha motorneurons, Interneurons and Renshaw cells, which form the basic control motor system for a single limb movement. Behaviour of each neuron is described by a differential equation, which provides it with a dynamic performance. This network is useful to control limb movements based in an antagonist pair of actuators, i.e. muscles for a human limb or electric motors or SMA fibers for machine applications. This antagonist structure has the main advantage that allows independent control of limb position and stiffness, which makes it suitable for applications where inertial load compensation is a critical factor. For the implementation of the neurons we have developed individual analog operators, like multipliers and integrators, which have been then joined to obtain the cell. The whole circuit works in current mode, and exhibits good performance in power disipation and bandwidth. The implementation of the network has been done in a 0.35um process from AMS. The layout size is 870 × 480 μm and the power dissipation is 14 mW, using a reference voltage of 3.3 volts. The applications in which this network canbe used fall in two broad cathegories. Firstly, in the development of human-machine interfaces capable to be used both in industry and in handicaped people and secondly in the development o neural controller for industrial robots, providing them with a compliance performance.

Current-mode implementation of processing modules in ART-based neural networks

This paper describes implementation of neural network processing layers using basic current-mode operating modules. The research work has been focused on the implementation of neural networks based on the Adaptive Resonance Theory, developed by S. Grossberg and G.A. Carpenter. The ART-based neural network whose operating modules have been choosen for development is the one called MART, proposed by F. Delgado, because of its complex architecture, auto--adaptive self-learning process, able to discard unmeaningful cathegories. Our presentation starts introducing the behaviour of MART with an analysis of its structure. The development described by this research work is focused on the monochannel block included in the main signal processing part of the MART neural network. The description of the computing algorithm of the layers inside a monochannel block are also provided in order to show what operational current-mode modules are needed (multiplier, divider, square-rooter, adder, substractor, absolute value, maximum and minimum evaluator...). Descriptions at schematic and layout levels of all the processing layers are given. All of them have been designed using AMS 0.35 micron technology with a supply voltage of 3.3 volts. The modules are designed to deal with input currents in the range of 20 to 50 microamps, showing a lineal behaviour and an output error of less than 10%, which is good enough for neural signal processing systems. The maximum frecuency of operation is around 200 kHz. Simulation results are included to show that the operation performed by the hardware designed matches the behaviour described by the MART neural network. For testing purposes we show the design of a monochannel block hardware implementation restricted to five inputs and three cathegories.