José Ángel Díaz-Madrid

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.

Low-Frequency CMOS Bandpass Filter for PIR Sensors in Wireless Sensor Nodes

In this paper, a CMOS fourth-order low-frequency bandpass filter for passive pyroelectric infrared sensors is presented. The sensor is intended for use in wireless sensor nodes, demanding strict low power requirements. The final use of these sensor nodes is an ambient assisted living system for elderly people living alone at home. A NICERA RE200B passive pyroelectric infrared sensor with a measured steady operation current of 3.5 μA has been used. The filter has been implemented cascading two biquad OTA-C filtering stages. OTA-C topology has been selected due to the extremely large time constant of the filter. The second-order stage circuit has been prototyped in a 0.35-μm CMOS process and power consumption is below 6.5 μW from a 3 V supply. A central frequency of 1.49 Hz, with Q = 0.5, and a gain of 45 V/V was achieved.

Accurate and reusable macromodeling technique using a fuzzy-logic approach

An approach for applying fuzzy logic for accurate analog circuit macromodel sizing is presented. In our proposed method, multiple adaptive neuro-fuzzy inference systems (MANFIS) are trained to predict the performance characteristics (gain, bandwidth) of a fully differential telescopic transconductance amplifier (OTA). The neuro-fuzzy computed characteristic values are in excellent agreement and one order of magnitude faster than those obtained from device level SPICE simulations. This technique allows the generation of accurate, efficient and reusable models of analog circuits. It is demonstrated and compared with other classical techniques like polynomial regression or artificial neural network approaches.

VHDL-AMD Model Of A 40M/s 12 Bits Pipeline ADC

In this paper we describe the structure and the VHDL-AMS high level model of a 40MSample/S 12 bit pipeline ADC. Design of high performance mixed signal circuits, like analog to digital converters require extensive simulations at different levels of analog design hierarchy. As we go deeper in details, down in the analog hierarchy, these simulations become more and more CPU time expensive and so, the verification stage previous to manufacturing of a typical ADC design cycle requires enormous amounts of time. The use of high level models in the design of complex mixed signal circuits allows the exploration of different solutions with high enough accuracy and fast simulations. Performance of the model developed in this paper is compared with postlayout extraction simulations of the ADC. Utility of VHDL-AMS behavioural model is demonstrated with the calculation of ADC performance subject to some design parameters variation

Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels

SUMMARY Some of the advantages of very high speed integrated circuits hardware description language for analog and mixed signal (VHDL-AMS) when used to describe analog circuits are its modeling capability and the speed of simulations, in comparison with device level simulators. However, VHDL-AMS does not allow one to complete in a systematic way the synthesis of an analog circuit from higher description levels of the design hierarchy to lower ones. This is due to the lack of CAD tools and methods for analog circuits, contrary to the situation of pure digital circuits. This is a serious drawback because it is an obstacle to its success in analog CAD tools. The proposal described in this article, on the basis of the use of parameterizable macromodels, allows a systematic and rapid translation from a VHDL-AMS description of analog circuits to schematic level-sized descriptions. Copyright

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing

High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35µm CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

ABSTRACT This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m2.

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

This paper presents a pipeline analog to digital converter (ADC) consisting of five stages with 2.5 effective bit resolution. Several techniques were combined for the reduction of the power consumption and to preserve the converter linearity. To reduce the power consumption, the circuit has two scaled operational transconductance amplifiers (OTAs), which are shared by the first four pipeline stages. The last fifth stage is a single decoder with 2.5 effective bits. Each OTA includes additional circuitry to adapt the power consumption according to the stage that uses the OTA. This technique changes the bias current depending on the stage in operation. The ADC was optimized to obtain 11-bit resolution with frequencies from 1 kHz to 10 MHz. The technology used to simulate the ADC is a 3.3 V 0.35 μm CMOS process and the circuit consumes 17.9 mW at 20 MSample/s sampling rate. With this resolution and sampling rate, it achieves 67.28 dB SNDR and 10.88 bit ENOB at 0.1 MHz input frequency. The Figure of Merit is 0.473 pJ/step.

Current mode CMOS synthesis of a motor---control neural system

This paper presents an analog CMOS implementation of a neural network based on a spinal cord model. The network is comprised by three pairs of cells, Alpha motoneurons, Interneurons and Renshaw cells, which form the basic control motor system for a single limb movement in a human being. Neurons behaviour is described by a differential equation, which provides it with a dynamic performance. This network is useful to control limb movements based in an agonist pair of actuators, i.e. muscles for a human limb or electric motors or SMA fibers for machine applications. This structure has the advantage that allows independent control of limb position and stiffness, which makes it suitable for applications where inertial load compensation is a critical factor.

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits

One of the typical applications of neural networks is based on their ability to generate fitting surfaces. However, for certain problems, error specifications are very restrictive, and so, the performance of these networks must be improved. This is the case of analog CMOS circuits, where models created must provide an accuracy which some times is difficult to achieve using classical techniques. In this paper we describe a modelling method for such circuits based on the combination of classical neural networks and electromagnetic techniques. This method improves the precision of the fitting surface generated by the neural network and keeps the training time within acceptable limits.