Hans-Martin Ritter

An off-chip ESD protection for high-speed interfaces

High-speed interfaces, e.g. for USB3.1 or HDMI2.0, require high system level ESD protection, typically 15 kV, without affecting signal integrity. This paper describes the development of a novel bipolar process and the design of a fast-switching, low-voltage clamping protection combining high protection capability with excellent signal integrity.

Gun tests of a USB3 host controller board

System level tests on a USB3 controller with on-board protection were found to yield irreproducible failure levels. A root cause analysis was performed using a combination of gun tests, TLP tests, and SEED simulation. It was found that an inductive current distribution between protection and SoC may explain the actual failure levels. Solutions are presented for effective on-board protection of USB3 controller boards. In addition, several gun artifacts were identified which prevent reproducible failure levels when using gun discharges. Instead, 50 Ω HMM testing yields results which correlate very well with SEED simulations.

Air-discharge testing of single components

The set-up for air discharge ESD testing on single components has been systematically investigated. Excellent repeatability can be achieved with an optimized set-up. The first peak is missing due to long risetimes. Surprisingly, the total charge in an air discharge pulse is larger than in a contact discharge.

Design of an On-Board ESD Protection for USB3 Applications

This paper describes the development of an on-board system level protection for high-speed cable connections (e.g., USB3) with 15 kV robustness and a signal transfer rate of up to 10 Gb/s. A dedicated bipolar process is developed, on a high-resistive substrate with optimized diffusion profiles and a special via-on-via metallization to meet the capacitance target of 0.25 pF. The protection is shown to work well with several popular USB3 chipsets.