Guido Notermans

Pitfalls when correlating TLP, HBM and MM testing

Correlation between human body model (HBM), machine model (MM) and transmission line pulse (TLP) testing is still under discussion. In this paper, it is shown that the lack of correlation is due to misinterpretations in the test results, due to the fact that soft and hard failures are often confused. This is illustrated by ESD results of test structures with grounded-gate NMOSTs and field oxide devices, measured according to HBM, MM and by means of TLP testing. It is shown that for a valid comparison, it is essential to combine electrical measurements with a thorough physical failure analysis in order to establish the failure signature. Once the failure signature and the current path are taken into account, a good correlation is found.

The effect of silicide on ESD performance

In this paper, a new model for localized breakdown in grounded gate NMOSTs under ESD stress is developed which accounts for the reduced ESD strength in silicided devices. The model explains the impact of a stabilizing drain resistance on second breakdown current for both silicided and unsilicided ESD protection NMOSTs.

On the use of n-well resistors for uniform triggering of ESD protection elements

N-well resistors are sometimes used to add series resistance to a grounded-gate NMOST protection device in order to ensure simultaneous triggering of multiple fingers. It turns out that such protections may fail far below their nominal ESD threshold depending on the particular layout. It is shown that n-well snapback plays a major role in the failure mechanism. Maximum ESD performance can be obtained by applying a simple design rule for the n-well geometry.

Designing HV active clamps for HBM robustness

Electrical measurements, physical damage analysis, and device simulation have proved that the drain junction breakdown voltage is the determining failure criterion for our HV active clamps. Using this criterion, the HBM and TLP robustness of such clamps can be accurately predicted by circuit simulation without the need for test silicon.

An off-chip ESD protection for high-speed interfaces

High-speed interfaces, e.g. for USB3.1 or HDMI2.0, require high system level ESD protection, typically 15 kV, without affecting signal integrity. This paper describes the development of a novel bipolar process and the design of a fast-switching, low-voltage clamping protection combining high protection capability with excellent signal integrity.

On the use of n-well resistors in ESD protections

N-well resistors are sometimes used to add series resistance to a grounded-gate NMOST protection device in order to ensure simultaneous triggering of multiple fingers. It turns out that such protections may fail far below their nominal electrostatic discharge (ESD) threshold depending on the particular layout. It is shown that n-well snapback plays a major role in the failure mechanism. Maximum ESD performance can be obtained by applying a simple design rule for the n-well geometry.

Gun tests of a USB3 host controller board

System level tests on a USB3 controller with on-board protection were found to yield irreproducible failure levels. A root cause analysis was performed using a combination of gun tests, TLP tests, and SEED simulation. It was found that an inductive current distribution between protection and SoC may explain the actual failure levels. Solutions are presented for effective on-board protection of USB3 controller boards. In addition, several gun artifacts were identified which prevent reproducible failure levels when using gun discharges. Instead, 50 Ω HMM testing yields results which correlate very well with SEED simulations.

Sub-miniature common mode filter with integrated ESD protection

A miniaturized common mode filter (CMF) for the USB 2.0 interface is presented. This novel design is built in a planar copper/polyimide process, allowing its combination with Electrostatic Discharge (ESD) protection diodes fabricated in bipolar semiconductor technology. This filter design provides strong common mode rejection in the GSM spectrum and the ESD protection diodes feature a very low dynamic resistance. The small size (1.34 mm × 0.95 mm) of the device makes it well suited for integration in modern mobile phone applications, to suppress electromagnetic interference (EMI) between a USB transmitter and the GSM receiver. Measurement data of mixed-mode S-Parameters and experimental results underline the EMI protection in the GSM downlink spectrum. The dynamic resistance is derived in transmission line puls (TLP) measurements. This combination of EMI filter and ESD protection outperforms conventional ferrite CMF with varistors.

Air-discharge testing of single components

The set-up for air discharge ESD testing on single components has been systematically investigated. Excellent repeatability can be achieved with an optimized set-up. The first peak is missing due to long risetimes. Surprisingly, the total charge in an air discharge pulse is larger than in a contact discharge.

High voltage resistant ESD protection circuitry for 0.5 /spl mu/m CMOS OTP/EPROM programming pin

This work introduces new high voltage resistant ESD protection circuitry for the programming pin of a nonvolatile one time programmable silicided 0.5 /spl mu/m CMOS device. TLM, HBM, and MM0.75 /spl mu/H ESD stress measurements of this new design resulted in latch-up resistant protection circuitry with an ESD performance of more than 8.0 kV HBM and 950 V MM0.75 /spl mu/H.