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Dive into the research topics where Hans Rohdin is active.

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Featured researches published by Hans Rohdin.


IEEE Transactions on Electron Devices | 1986

A MODFET dc model with improved pinchoff and saturation characteristics

Hans Rohdin; P. Roblin

We present an analytical dc model for the MODFET that offers several improvements over existing models. An enhanced version of the model makes use of a new approximation of the two-dimensional electron gas (2DEG) concentration versus gate-to-channel voltage, which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. Even in this more accurate model there are no complicated numerical calculations involved; at most what is required is finding a single root of a function of one variable. We propose an electron velocity-field curve that combines the observed field-dependent mobility in the 2DEG, and the sharp velocity saturation in GaAs. We use a two-region Grebene-Ghandhi model with floating boundary for the channel. The quasi-linear region on the source side is treated by the gradual channel approximation and extends toward the drain up to a point where the field reaches its threshold for velocity saturation. Between this point and the drain-side end of the channel, the potential is determined by the two-dimensional Poisson equation in the AlGaAs region. The resuitingI-Vcharacteristics and their slopes are continuous. The model predicts a maximum transconductance and a finite intrinsic output conductance in the saturated region, two features experimentally observed but not predicted by previous models. In the limit of very short gate lengths the model approaches the saturated velocity model, while in the limit of very long gate lengths it approaches the classical gradual channel model.


IEEE Transactions on Electron Devices | 1998

Interfacial gate resistance in Schottky-barrier-gate field-effect transistors

Hans Rohdin; Nick Moll; Chung-yi Su; Gregory S. Lee

We discuss in depth a previously overlooked component in the gate resistance R/sub g/ of Schottky-Barrier-Gate FETs, in particular, 0.1-/spl mu/m gate-length AlInAs/GaInAs MODFETs. The high-frequency noise and power gain of these FETs depend critically on R/sub g/. This has been the motivation for the development of T-gates that keep the gate finger metallization resistance R/sub ga/ (proportional to the gate width W/sub g/) low, even for very short gate length L/sub g/. R/sub ga/ increases with frequency due to the skin effect, but our three-dimensional (3-D) numerical modeling shows conclusively that this effect is negligible. We show that the always larger-than-expected R/sub g/ is instead caused by a component R/sub gi/ that scales inversely with W/sub g/. We interpret R/sub gi/ as a metal-semiconductor interfacial gate resistance. The dominance of R/sub gi/ profoundly affects device optimization and model scaling. For GaAs and InP-based SBGFETs, there appears to exist a smallest practically achievable normalized interfacial gate resistance r/sub gi/ on the order of 10/sup -7/ /spl Omega/ cm/sup 2/.


international conference on indium phosphide and related materials | 1997

Drain resistance degradation under high fields in AlInAs/GaInAs MODFETs

Arlene Wakita; Hans Rohdin; Chung-yi Su; Nick Moll; A. Nagy; Virginia M Robbins

Lattice-matched AlInAs/GaInAs modulation-doped FETs (MODFETs) demonstrate excellent high-frequency, small-signal performance. However, high-power, large-signal applications of these devices may be limited. Impact ionization and tunneling reduce the breakdown voltage, which limits the upper end of the output voltage swing, thus reducing the output power. Our results indicate that the lower end of the voltage swing (knee voltage) is also degraded by increased drain resistance when impact ionization occurs. In this work, we correlate R/sub d/ degradation in the AlInAs/GaInAs material system to the presence of impact ionization. The magnitude of R/sub d/ degradation depends on the applied drain bias and drain current. These factors affect the degree of impact ionization, and thus the extent of the degradation. Since R/sub d/ increases and R/sub s/ does not, only the high field side of the FET is affected. This increase in R/sub d/ is attributed to a wider carrier depletion region between the gate and drain after stress, which results in reduced device performance.


international conference on indium phosphide and related materials | 1997

Semi-analytical analysis for optimization of 0.1-/spl mu/m InGaAs-channel MODFETs with emphasis on on-state breakdown and reliability

Hans Rohdin; Chung-Yi Su; Nick Moll; Arlene Wakita; A. Nagy; V. Robbins; M. Kauffman

We have measured and analyzed the bias limitations of our 0.1-/spl mu/m In/sub 53/Ga/sub 47/As-channel MODFETs. A semi-analytical model allows us to correlate a major degradation mechanism, the increase in drain resistance to impact ionization in the narrow-bandgap channel. We find, as others have, that this mechanism also determines the on-state breakdown voltage BV/sub DS//sup (on)/, and thus limits the operating regime. The modeling predicts the shape of BV/sub DS//sup (on)/ vs. I/sub D/ and shows that the off-state breakdown voltage is irrelevant for practical load-lines. BV/sub DS//sup (on)/(I/sub D/) deviates markedly from a constant power locus. In fact, it tends to have a flat minimum BV/sub DS//sup (on,min)/ (corresponding to maximum impact ionization current) near the I/sub D/ of maximum transconductance. BV/sub DS//sup (on,min)/ becomes the most significant measure of FET breakdown. Most of our device variations have tended to produce a constant-power trade-off of BV/sub DS//sup (on,min)/ with its associated I/sub D/, in contrast to the non-constant-power locus of BV/sub DS//sup (on)/(I/sub D/) The model predicts both trends well.


IEEE Transactions on Electron Devices | 1990

Reverse modeling of E/D logic submicrometer MODFETs and prediction of maximum extrinsic MODFET current gain cutoff frequency

Hans Rohdin

A method for estimating the source resistance, fringe capacitance, gate length, and effective saturation velocity from the microwave Y-parameters of MODFETs with known vertical structure is discussed. The scheme is applied to a variety of MODFETs fabricated on molecular-beam-epitaxial (MBE) material using a submicrometer enhancement/depletion- (E/D-) mode IC process. More than 100 MODFETs were measured and analyzed. Both the values and variances of the extracted parameters are very physical. In particular, it is found that the extracted saturation velocity (1) is independent of the gate length in the regime studied (0.25-0.91 mu m); (2) is rather independent of process and threshold voltage variations; (3) is marginally higher when the Al mole fraction is increased from 20% to 28%; (4) is not significantly higher in pseudomorphic InGaAs than in GaAs; and (5) is quite a bit higher than is often assumed or extracted, with a value close to the stationary peak velocity in undoped GaAs. There is little sign of overshoot above this limit. Using the extracted peak velocity and a simple analytical MODFET model, the extrinsic current gain cutoff frequency (f/sub Tx/) is predicted well in the gate-length regime studied. >


Japanese Journal of Applied Physics | 1999

Low-Noise Bias Reliability of AlInAs/GaInAs Modulation-Doped Field Effect Transistors with Linearly Graded Low-Temperature Buffer Layers Grown on GaAs Substrates

Arlene Wakita; Hans Rohdin; Virginia M. Robbins; Nick Moll; Chung–Yi Su; Avelina Nagy; David Basile

The low-noise bias reliability of 0.1 µm T-gate Al0.48In0.52As/Ga0.47In0.53As modulation-doped field effect transistors (MODFETs), grown on GaAs was investigated. Al0.48In0.52As/Ga0.47In0.53As MODFETs were grown on mismatched GaAs substrates by the insertion of a compositionally linearly-graded low-temperature buffer (LGLTB) layer. Transmission electon microscopy (TEM) analysis of the layers indicates that the majority of the defects are confined to the buffer layer. Although the LGLTB layer is highly defective, there is no indication that the low-bias reliability of these devices is compromised. MODFETs with a LGLTB layer show reliability under high temperature operating life (HTOL) tests at a drain bias of 1 V and 200 mA/mm, comparable to reported MODFETs grown lattice-matched to InP. The extrapolated mean-time-to-failure (MTTF), based on the drift of the zero-gate bias current, Idss, at temperatures of 200 to 240°C, exceeds 106 h at a channel temperature of 125°C. The drift in Idss arises primarily from a positive shift in threshold voltage. The low-bias Rd degradation behavior of these devices is also similar to devices grown on InP.


international conference on indium phosphide and related materials | 1998

Low-noise bias reliability of AlInAs/GaInAs MODFETs with linearly graded low-temperature buffer layers grown on GaAs substrates

Arlene Wakita; Hans Rohdin; Virginia M Robbins; Nick Moll; Chung-yi Su; A. Nagy; D.P. Basile

AlInAs/GaInAs MODEETs lattice-matched to InP have been shown to be reliable at low bias (V/sub ds/=0.75 to IV) for low-noise applications. Mean-times to failure (MTTF) from 10/sup 5/ to 10/sup 7/ hrs., based on various failure criteria, have been reported for lattice-matched FETs. To improve manufacturability of these FETs we have fabricated 0.1 /spl mu/m T-gate AlInAs/GaInAs MODFETs on mismatched GaAs substrates by the insertion of a compositionally linearly graded low-temperature buffer (LGLTB) layer. In this work, we demonstrate that such FETs show comparable reliability at low bias under high temperature operating life (HTOL) tests to FETs on InP. Although the LGLTB layer is highly defective, there is no indication that the low-bias reliability of these devices is compromised. Our AlInAs/GaInAs MODFETS, grown on GaAs, have an extrapolated MTTF, based on I/sub dss/ drift, exceeding 10/sup 6/ hours at a channel temperature of 125/spl deg/C.


international symposium on circuits and systems | 1990

Self-aligned contact submicron E/D MODFET IC process: device characteristics and simple circuit applications

Hans Rohdin; Avelina Nagy; A. Fischer-Colbrie; Chris Kocot; Rolf Jaeger

A high-speed, low-power GaAs enhancement/depletion (E/D) IC process for MSI applications (10/sup 3/ devices) is described. The process relies on high-quality molecular-beam-epitaxy (MBE)-grown modulation-doped wafers, and an etch-stop reactive ion etch (RIE) process that preserves the inherent uniformity and control achievable with this growth technique.<<ETX>>


[1991] GaAs IC Symposium Technical Digest | 1991

A 23.6 GHz sub-1/2- mu m E/D MODFET divide-by-32/64 static prescaler

Hans Rohdin; J. Straznicky; H. Jekat; A. Nagy; A. Fischer-Colbrie; D. Mars; R. Jaeger

An application-ready prescaler with performance competitive with state-of-the-art R&D dividers is reported. It was designed to be a high-performance replacement for standard ECL parts in instruments. It is fabricated in a proven self-aligned contact sub-1/2-micron GaAs-based E/D-MODFET IC process which utilizes side-wall-spacer self-alignment technology to obtain 0.3-0.5 mu m gate length with conventional high-throughput contact lithography. With pseudomorphic InGaAs channels the authors have demonstrated 30 MHz-23.6 GHz prescaler operation at room temperature. The performance improves at 0 degrees C, while at 70 degrees C the upper frequency typically drops by 2 GHz. Correct high-speed pulsed-mode operation requires (1) presetting which does not degrade the performance and (2) suppression of self-oscillation during quiet periods between pulse bursts.<<ETX>>


Solid-state Electronics | 1999

A 0.1-μm MHEMT millimeter-wave IC technology designed for manufacturability

Hans Rohdin; Arlene Wakita; Avelina Nagy; Virginia M Robbins; Nick Moll; Chung-yi Su

Abstract We describe and discuss our approach to improved manufacturability of millimeter-wave InP-type HEMT IC technology. The main ingredients are the use of (1) GaAs (rather than InP) as substrate, with a buffer that grades the lattice constant to that of the high-mobility Ga 0.47 In 0.53 As channel; (2) low-resistance non-alloyed ohmic contacts with good reliability and reproducibility; (3) an e-beam process that produces 0.1-μm T-gate fingers with one exposure and (4) two-step selective etching of the gate trough for good uniformity. The process is compatible with standard GaAs FET IC front and back end unit processes, including backside vias. The yield, uniformity and performance of devices and circuits made on this metamorphic (MHEMT) material are consistently as good as those we get using InP substrates. The reliability of our devices, whether made on GaAs or InP substrates, is limited by impact ionization in the channel, which has also been linked to R d -degradation and burnout. At low-noise drain bias ( V d =1 V), where the impact ionization is small, we have demonstrated reliability, i.e. extrapolated MTTF at 125°C channel temperature is >10 6 h. This is as good as FETs made on InP substrates.

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