Hanspeter Schmid

Navigation grade MEMS accelerometer

This paper reports on a high performance navigation grade MEMS servo accelerometer targeted at inertial applications. Reported results are for a bulk MEMS capacitive sensor with 11g full scale over a 300 Hz bandwidth interfaced with a highly optimized servo-loop 5^th-order sigma-delta electronic. Measurements demonstrate a long-term bias stability of +/−0.2mg, a second order non-linearity K2 ≪5 µg/g², an in-band noise floor of 1 µg/√Hz and a Dynamic Range over 1 Hz bandwidth of 22 bits.

Fundamental frequency limitations in current-mode Sallen-Key filters

Single-amplifier filter biquads and especially Sallen-Key filters are widely used to build higher-order filter cascades. This paper investigates high-frequency current amplifier non-idealities and their effects on all-pole Sallen-Key filter biquads. It is shown that a non-ideal current amplifier input causes parasitic zeros in the filter transfer function, and thus imposes fundamental limitations on the realisable pole frequency. Design equations are given, providing compensation for their amplifiers port impedances and its phase lag, by predistortion of the component values. It is also shown how design specifications for a current-amplifier can be derived from the filter specification, minimising the amplifiers power dissipation. Finally, a video-frequency lowpass filter is discussed.

A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5 th -order ΔΣ loop

This paper presents a 5^th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5^th-order filter having a 2^nd-order analog and a 3^rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3^rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.

Measuring a Small Number of Samples, and the 3v Fallacy: Shedding Light on Confidence and Error Intervals

Many solid-state circuits papers today report the mean and the standard deviation of measurement results obtained from a small number of test chips and then compare them with numbers other authors obtained. Almost none of them discuss confidence intervals, ranges of values for that standard deviation within which the true value lies with a certain probability. Many implicitly assume that the range would contain all but 0.27% of chip samples to be expected in volume production. This is incorrect even if it is certain that the measured quantity is exactly normal distributed.

The current-feedback OTA

The current-feedback OTA (CFB OTA) recently appeared in a new classification of operational amplifiers. It is dual to the operational floating amplifier (OFA), so all OFA circuits can readily be transposed into CFB OTA circuits. This paper discusses the theoretical basis of the CFB OTA, shows its relation to the OFA, and compares their performance in a simple V-I converter by showing how both can be built with the same two transistor stages. The advantages and disadvantages of the CFB-OTA implementation are discussed as well, but the main advantage of introducing the CFB OTA is that its introduction is virtually for free: most current opamps from the literature can be concerted into CFB OTAs by re-wiring their input stage, without adding or re-sizing a single transistor.

A navigation-grade MEMS accelerometer based on a versatile front end

This paper presents a MEMS-based 5^th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5^th-order filter having a 2^nd-order analog and a 3^rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front-end is programmable. The developed ASIC comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit internally non-linear flash ADC. The latter drives a 3^rd-order digital filter which can be configured for different sensor parameters in order to ensure overall loop stability and to optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300-Hz bandwidth.

A charge-pump-controlled MOSFET-C single-amplifier biquad

The spurious-free dynamic range (SFDR) of a MOSFET-C filter can be increased greatly by generating its tuning voltage with a charge pump. In this paper, we apply this technique to build a Sallen-and-Key lowpass filter with a pole frequency of 24 MHz and a pole Q of 3. It has an SFDR better than 50 dB and consumes 16 mW from a 3.3 V supply. Implemented with a double-poly triple-metal 0.6-/spl mu/m CMOS process, it covers an area of only 0.11 mm/sup 2/. In addition to a description of the filter and the charge pump, we also discuss linear and non-linear clock feed-through from the charge pumps own ring oscillator, and derive a formula for the optimum voltage swing at the MOSFET-C network nodes.

A tunable, video-frequency, low-power, single-amplifier biquadratic filter in CMOS

In this paper, a tunable single-amplifier biquadratic lowpass filter is presented. It consists of one balanced low-gain current amplifier and a second-order MOSFET-C feedback network. The filter was integrated in a double-poly 0.6 /spl mu/m CMOS process and operates from a 3.3 V power supply. The pole frequency is tunable from 15.2 to 17.2 MHz, the pole Q is 3, the spurious-free dynamic range is at least 60 dB, and the filter consumes only 2.4 mW per pole. Furthermore, the active area used per pole is only 0.06 mm/sup 2/. The filter is well suited for low-power video-frequency applications, and demonstrates that the MOSFET-C filter technique can be applied successfully to filters other than those based on integrator-connected topologies.

An internally non-linear ADC for a ΣΔ accelerometer loop

If an analog-to-digital converter (ADC) is used within a ΣΔ converter such that the loop filter is mixed signal, then the ADC does not need to have the full resolution of the ΣΔ converter, and its input values will not be uniformly distributed over the input range. In this paper, we argue that the best input distribution to use as a general model is the maximum-entropy distribution (for location parameters: the Gaussian distribution). We then describe an externally linear ADC with non-linearly spaced decision boundaries implemented in 0.6μm CMOS and show measurement results of a 19-bit dynamic range ΣΔ accelerometer loop inside which the ADC reaches more than the required 7-bit performance with only 26 decision levels.

Tutorial 13: Analog Circuit Design on Digital CMOS : Why it is difficult, and which ideas help?

This tutorial covers a wide range of small things an analog-IC designer should know to find a path through all the challenges of designing analog circuits on standard digital CMOS processes. The three main topics are: signal integrity (handling noise, treating signal ground, dealing with parasitic modulated feedback in switched circuits) unconventional use of standard parts (exploiting weak inversion, exploiting small dimension effects, unconventional uses of switched-capacitor techniques), and the question whether to feed back or not to feed back (self-biased and regulated current mirrors for gain enhancement, reduction of power consumption with low-feedback circuits.) Most examples come from low-voltage and low-noise broad-band applications, but RF is not covered. Many of the tricks were proven in industrial chips by the author or by people he knows, and will therefore need to be presented without explicit references.