Alex Huber

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2times-oversampling phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate <10-12 was verified up to 38 Gb/s using a 27 -1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90 nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 mm2.

A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5 th -order ΔΣ loop

This paper presents a 5^th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5^th-order filter having a 2^nd-order analog and a 3^rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3^rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.

5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS

This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate <10-12 was verified up to 38 Gb/s using a 27-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and reference clock.

Measuring a Small Number of Samples, and the 3v Fallacy: Shedding Light on Confidence and Error Intervals

Many solid-state circuits papers today report the mean and the standard deviation of measurement results obtained from a small number of test chips and then compare them with numbers other authors obtained. Almost none of them discuss confidence intervals, ranges of values for that standard deviation within which the true value lies with a certain probability. Many implicitly assume that the range would contain all but 0.27% of chip samples to be expected in volume production. This is incorrect even if it is certain that the measured quantity is exactly normal distributed.

Design and phase noise analysis of a multiphase 6 to 11 GHz PLL

This paper presents the design, the phase noise analysis and measurement results of a fourth-order phase-locked loop (PLL) circuit. The PLL is composed of a four-stage inductorless ring oscillator, a 1/16-divider, phase-frequency detector (PFD), charge pump and loop filter, which all are fully differential circuits. A tuning range of 6 to 11 GHz is achieved using delay interpolation elements in the ring oscillator. For jitter minimization, we analyze the noise contribution of each building block, identify the largest noise contributors, and evaluate the total PLL phase noise in s- and z-domain. The measured RMS jitter of 18 mUI agrees well with the predicted value of 15 mUI from our noise analysis. The PLL is fabricated in 90-nm bulk CMOS, consumes a current of 45mA at 1.1V and occupies an area of 0.1 mm2.

Low Power Sampling Latch for up to 25 Gb/s 2x Oversampling CDR in 90-nm CMOS

A sampling latch for full-, half and quarter-rate clock and data recovery circuits at data rates of 12.5 Gb/s, 20 Gb/s and 25 Gb/s, respectively, achieving a bit error rate lower than 10-12 is presented. The circuit is implemented in a 90-nm CMOS technology. The master-slave D-FF including peaking inductors consumes only 1 mW of power and requires a snail area of 30times20 mum2

A highly sensitive frontend IC for very robust capacitive vortex flowmeter sensors

This paper presents a capacitive sensor interface IC for vortex flow measurements. With this interface, we can measure flows down to half the minumum flow speed of the state of the art, for media temperatures up to 400°C and pressures up to 200 bar in pipes from 15mm up to 300mm diameter, even in the presence of mechanical vibrations, for media ranging from air over oil to mercury. The mechanical sensor used is very robust in the presence of steam hammers. The sensor IC was realized in 0.35μm CMOS and operates over a temperature range of -50Ω125°C. It adds input-referred noise far below the kT/C noise of the sensor, 1.17 aF/√Hz at fs = 128 kHz. The IC consumes 1.5mA from a 3.3V supply and has an area of 10mm2. The main signal processing problems to solve were the compensation of time-varying offsets up to 8 pF while measuring 60 aF, and the digital detection of signal frequencies at 1.15 dB SNR, done by adaptive filtering. The sensor IC has a production yield of 96.5 %.

The 3v Fallacy: Measuring a Small Number of Samples

Many solid-state circuits papers today report the mean n and the standard deviation v of measurement results obtained from a small number of test chips and then compare them with numbers other authors obtained. Almost none of them discuss confidence intervals, ranges of values for that standard deviation within which the true value lies with a certain probability. Many implicitly assume that the n! 3v range would contain all but 0.27% of chip samples to be expected in volume production. This is incorrect even if it is certain that the measured quantity is exactly normal distributed.