Hao-Hsiang Chuang

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Critical Concerns in Soldering Reactions Arising from Space Confinement in 3-D IC Packages

Six critical issues relating to interfacial reactions arising from space confinement in 3-D integrated-circuit (3-D IC) packaging are presented in this paper. The first issue arises from the concern that intermetallics (IMCs) may occupy a large portion of the solder joint volume. It will be demonstrated that this concern is real even for Ni under bump metallurgy (UBM) or surface finish, which reacts very slowly with solders. The second issue relates to impingement and ripening of IMC grains. When IMCs occupy a large portion of a joint, the IMC grains growing from the opposite sides of a joint will eventually touch each other. The morphology evolution from this point on determines the final microstructure of a joint. Structural defects might form as a result of the impingement and ripening of IMC grains. The third issue is the rise of impurity concentration due to solder consumption. Many of the impurities in solders, such as those from electroplating, are not soluble in IMCs. As Sn reacts to form IMCs, these impurities are rejected from IMCs into the remaining solder. Consequently, the concentrations of these impurities increase with the progress of reaction. Eventually, these impurities are trapped between IMCs growing from the opposite directions. The impact of these trapped impurities on the properties of solder joints is an important issue. The fourth issue is similar to the third except that the role of impurities is replaced by inert alloy elements of solders. The most obvious element is Ag. The fifth issue arises from the fact that, as the size of a joint becomes smaller, the surface-area-to-volume ratio increases. This makes the impact of thin-film layers on UBM and surface finish become ever higher. One well-known element is Au. The so-called Au embrittlement issue may become relevant again. The last issue is the volume shrinkage from chemical reactions. Internal stress or structure defects may form because of this shrinkage. Experimental evidence will be used in this paper to illustrate these six issues, and the implications of these issues will be discussed.

Design and Modeling of a Stopband-Enhanced EBG Structure Using Ground Surface Perturbation Lattice for Power/Ground Noise Suppression

Based on the ground surface perturbation concept, a novel stopband-enhanced electromagnetic-bandgap (EBG) structure has been proposed to suppress the power/ground noise on a three-layer package. This structure consists of a coplanar periodic pattern on the top layer, a ground plane on the third layer, and a ground surface perturbation lattice on the second layer with eight vias connecting to the ground plane. By designing the dimension and via numbers, the ground surface perturbation lattice can significantly enhance the stopband bandwidth. A generic 1-D circuit model is proposed for the three-layer EBG structure. The reason why the proposed structure can possess wider stopband will be explained. Several test samples are fabricated. The agreement of the stopband between the circuit model and measured results are good.

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

A Novel Ground Resonator Technique to Reduce Common-Mode Radiation on Slot-Crossing Differential Signals

By symmetrically placing a pair of open-stub resonators on the slotted reference plane, the radiated emission induced by common-mode noise crossing the slot can be effectively suppressed. The ground resonators provide a shorting path below the slot-crossing differential line for common-mode return current around the resonant frequency and thus avoid the noise to excite the slot line. Based on this idea, test samples with the proposed structure are fabricated on FR4 substrate. The experimental and numerical results show that the radiated emission caused by the slot-crossing common-mode noise can be effectively reduced at least 5 dB in the frequency range from 2.16 to 3.44 GHz by the ground resonators. It is a low cost and effective solution for reducing the common-mode radiation for the slot-crossing high-speed differential signals on high density package or PCB.

A Magnetic-Field Resonant Probe With Enhanced Sensitivity for RF Interference Applications

High-sensitive field probes are highly desirable for radio-frequency (RF) interference studies, where ultralow noise levels are of interest. By incorporating an LC resonant circuit in a differential-loop probe, together with a Marchand balun, a magnetic-field probe with enhanced sensitivity is developed. Its equivalent circuit model and design methodology are established. The design is validated by measurements. The measured relative sensitivity in terms of |S21| of the proposed probe increases by approximately 8.63 dB at the resonant frequency of 1.575 GHz compared to that of a conventional design. The advantage of the proposed probe is validated through its application in the measurement of a microstrip trace and a real-world cell phone design.

Novel Differential-Mode Equalizer With Broadband Common-Mode Filtering for Gb/s Differential-Signal Transmission

In high-speed differential signal transmission, signal integrity at the receiving end is mainly determined by high quality of the differential-mode signal and good suppression of the common-mode noise. In this paper, an innovative circuit with dual function of the differential-mode equalizer and common-mode filter (DME-CMF) is proposed. The differential-mode and common-mode characteristics of the proposed structure are discussed separately with their corresponding half-circuit model. Based on the proposed design methodology for the DME-CMF and the presented structure realizing the DME-CMF with a two-layer printed circuit board, a set of design parameters are determined for 8-Gb/s differential transmission and utilized in the fabrication of test boards. The frequency-domain and time-domain measurements of the test board successfully demonstrate the effectiveness of the proposed structure.

Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory

The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

A solution for reducing the signal distortion in SiO2-coated through silicon vias (TSVs) is proposed. The mechanism can be explained by using a verified equivalent circuit model of a four-TSV system. Based on this circuit model, the phenomena that larger thickness of dielectric layer causes lower slow-wave factor (SWF), smaller insertion loss and smaller crosstalk level can be observed. With the aid of ajinomoto-build-up-film-coated (ABF-coated) TSVs, the solution can be implemented. The insertion loss is 3 dB better, the near-end crosstalk is 5 dB better, and the far-end crosstalk is 25dB better than conventional SiO2-coated TSVs at 2 GHz. Measurement results are also given. Good consistency can be seen, and can support the conclusion of the simulation results.