Yi-Chang Lu

Thermal modeling for 3D-ICs with integrated microchannel cooling

Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs. Validation results show the proposed thermal model achieves more than 400× speed up and only 2.0% error in comparison with a commercial numerical simulation tool. We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage. We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction. We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC. It could result in up to 25°C peak temperature difference according to our experiments.

Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling

Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3-D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3-D ICs. A combination of the microchannel thermal-wake function and the channel merging technique achieves more than 3300× speedup with less than 5% error in comparison with a commercial numerical finite volume simulation tool. With the proposed model, we characterize thermal behaviors of microchannel-cooled 3-D ICs and compare them with the case of conventional air-cooled 3-D ICs. We also demonstrate thermal-aware placements using our thermal model. It shows that the proposed model can be used to reduce peak temperatures, which is considered important for 3-D IC designs.

Growth of CuAl intermetallic compounds in Cu and Cu(Pd) wire bonding

In this study, Cu wire bonds are aged at 150, 175, 250, and 350 °C for time ranging from 5 min to 2000 h. The top temperature of 350 °C is chosen to have the fastest kinetics, while maintaining the same types of stable intermetallics (IMCs) according to the Al-Cu binary phase diagram. Two types of Cu wire are used, including bare Cu wire and Pd coated Cu wire. To avoid possible damages from conventional mechanical polishing processes, all cross-sections are carried out by using an Ar ion beam cross-section polisher. Observations are carried out using a field-emission scanning electron microscope. The compositions of IMCs are determined by using a state-of the-art field-emission electron microprobe. According to the results of this study, in the as-bonded condition, the IMC formed is CuAl2. Its morphology is island-type and covers only a small percentage of the interface. During aging, the growth directions of IMCs are both lateral and perpendicular to the interface. At the lowest temperature (150 °C), the growth of IMCs is very slow. Even after 2000 h of aging, a large portion of Al remains un-consumed, and the IMCs formed are CuAl2 and CuAl. The growth rate increases very rapidly with temperature. At the highest temperature (350 °C), most of the Al is consumed after only 30 min of aging, and a thick layer of Cu3Al2 form over CuAl and CuAl2. Detailed morphological evolutions of IMCs for all temperatures are described. The Pd atoms in Pd-coated Cu wire do not participate in the interfacial reaction, and have no marked effect on the growth rate of IMCs. There is no detectable Pd signal in the IMCs. With the formation of IMCs, the Pd atoms are rejected into Cu in front of the IMCs.

ABF-Based TSV Arrays With Improved Signal Integrity on 3-D IC/Interposers: Equivalent Models and Experiments

An Ajinomoto-Build-up-Film (ABF) material is proposed to manufacture through-silicon vias (TSVs) with better signal integrity and lower cost than that of conventional TSVs. The unique advantage of the ABF-based TSVs is that the isolation layer can be thicker than the conventional TSVs, and thus both the insertion loss and crosstalk of the ABF-based TSVs can be improved. An equivalent circuit model is given to predict the electrical behavior of the TSVs and to explain how ratio of the isolation layers thickness to the radius affects the signal integrity. The concept is demonstrated both in frequency- and time-domain simulations. Finally, a test sample of nine-stack ABF-based TSVs is fabricated and assembled. The scanning electron microscope figure supports that the ABF-based TSVs have a thickness-to-radius ratio of 0.667, which is much higher than the conventional TSVs ratio of about 0.1. The measurements also support the simulated results from the equivalent circuit model.

Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

An equivalent circuit model to characterize the crosstalk strength in multiple TSVs is newly proposed. In this model, all the values of lumped elements in the model are given in closed-form formulas. Therefore, the computation effort for constructing the model of multiple TSVs is much lower than other previous works. The accuracy is verified by the measurement for a nine stacked silicon chips and the full-wave simulation results. The proposed model is then utilized to the design for crosstalk mitigation. With the advantages of smaller occupied area (lower cost), a rhombus-grounded Faraday cage design is recommended with lower cost and similar performance compared to conventional Faraday cage concept.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are <; 5%.

Architecture for next-generation massively parallel maskless lithography system (MPML2)

Electron-beam lithography is promising for future manufacturing technology because it does not suffer from wavelength limits set by light sources. Since single electron-beam lithography systems have a common problem in throughput, a multi-electron-beam lithography (MEBL) system should be a feasible alternative using the concept of massive parallelism. In this paper, we evaluate the advantages and the disadvantages of different MEBL system architectures, and propose our novel Massively Parallel MaskLess Lithography System, MPML2. MPML2 system is targeting for cost-effective manufacturing at the 32nm node and beyond. The key structure of the proposed system is its beamlet array cells (BACs). Hundreds of BACs are uniformly arranged over the whole wafer area in the proposed system. Each BAC has a data processor and an array of beamlets, and each beamlet consists of an electron-beam source, a source controller, a set of electron lenses, a blanker, a deflector, and an electron detector. These essential parts of beamlets are integrated using MEMS technology, which increases the density of beamlets and reduces the system cost. The data processor in the BAC processes layout information coming off-chamber and dispatches them to the corresponding beamlet to control its ON/OFF status. High manufacturing cost of masks is saved in maskless lithography systems, however, immense mask data are needed to be handled and transmitted. Therefore, data compression technique is applied to reduce required transmission bandwidth. The compression algorithm is fast and efficient so that the real-time decoder can be implemented on-chip. Consequently, the proposed MPML2 can achieve 10 wafers per hour (WPH) throughput for 300mm-wafer systems.

An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node

In this paper, a new asynchronous circuit design is presented. A special technique that enables fast forwarding is applied to the circuits, and the forward transition improves to less than 2. The handshaking process and cycle time of the asynchronous circuits are analyzed, and its performance and functionality under fabrication and temperature variations are evaluated through Monte Carlo simulations in 65 nm technology. The proposed asynchronous circuits are compared to the static and domino logic circuits to assess their delay variations and functional success rates.

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage. Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design. In this paper, TCAD device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors. It is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region. A new EGL extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity. Preliminary results verified by TCAD simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved. The method is readily applicable to calibration with real silicon data.