Haolu Xie

A review on RF ESD protection design

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.

A mixed-mode ESD protection circuit simulation-design methodology

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.

A varying pulse width 5 th -derivative gaussian pulse generator for UWB transceivers in CMOS

A fully integrated, ultra low-power, varying pulse width fifth-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18 mum CMOS technology is reported for 3-10 GHz impulse ultra wideband (UWB) transceivers. The fifth-order derivative Gaussian pulse generator circuit consists of four parallel Gaussian pulse formation blocks and an output stage. It can generate UWB pulse signals with adjustable pulse width ranging from 240 picoseconds to a few nanoseconds. Measurement results show very short UWB pulses with amplitude of 51 mV and an ultra low power consumption of 3.6 mW at 100 MHz pulse repeating frequency (PRF) with 1.8 V power supply voltage. This pulse generator fully complies with FCC UWB power mask.

Characterizing diodes for RF ESD protection

A diode string as an electrostatic discharge (ESD) protection structure for RF ICs is attractive because of its reduced total parasitic capacitance. This letter reports a comprehensive RF characterization of diodes for RF ESD protection, including S-parameters, parasitic capacitance, and resistance. It is found that a two- or three-diode string may be an optimal RF ESD protection solution due to the balanced overall performance, including ESD protection level, total size, and ESD-induced parasitic effects, etc. An optimized two-diode string for 5 kV ESD protection features a 108.5 fF parasitic capacitance at 2.4 GHz, and is 3680 /spl mu/m/sup 2/ in size. The design was implemented in a commercial 0.35-/spl mu/m BiCMOS technology.

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractors efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.

1.8 pJ/Pulse Programmable Gaussian Pulse Generator for Full-Band Noncarrier Impulse-UWB Transceivers in 90-nm CMOS

This paper presents a single-chip ultralow power programmable Gaussian pulse generator (PG) designed and implemented in the 90-nm CMOS for 3.1-10.6 GHz full-band impulse-radio ultrawideband (UWB) transmitters. Measurement shows that this novel simple two-inverter-based PG achieves the lowest reported power dissipation of merely 1.8 pJ/pulse with a 100-MHz pulse-repeating frequency at 1-V supply, extremely short and programmable pulsewidth ranging from 150 to 350 ps while covering the full 3.1-10.6 GHz UWB spectrum, and a very small area of 0.0068 mm2. It supports up to 6 Gb/s data rate for UWB wireless streaming. A new Federal-CommunicationCommission-aware Gaussian PG design optimization method is discussed and verified experimentally.

FCC-EIRP-aware UWB pulse generator design approach (invited)

This paper reviews a systematic method for design and analysis of high-order Gaussian pulse generators (PG) for carrier-free impulse-radio ultra wideband (IR-UWB) transceivers, which enables to achieve PG performance optimization and FCC effective isotropic radiated power (EIRP) compliance simultaneously. The new FCC-EIRP-aware design method is verified experimentally using Gaussian PG circuits with different derivative orders designed in CMOS.

A Broadband CMOS Multiplier-Based Correlator for IR-UWB Transceiver SoC

A multiplier-based correlator is an important component for impulse radio ultra-wideband (IR-UWB) receiver. Classified as correlation-type demodulator, this type of correlator uses correlation-type demodulation. This paper reports design and implementation of a fully integrated low-power broadband multiplier-based correlator for a 3.1-10.6 GHz full-band UWB receiver in 0.18 mum CMOS that consists of an UWB multiplier and a first-order RC integrator with a 200 MHz bandwidth Measurement results confirm the correlation-type demodulation function and achieve a conversion gain of 0 dB, noise figure of 8.2 dB and power consumption 52 mW for the UWB multiplier.