Xiaokang Guan

A review on RF ESD protection design

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.

A mixed-mode ESD protection circuit simulation-design methodology

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.

Characterizing diodes for RF ESD protection

A diode string as an electrostatic discharge (ESD) protection structure for RF ICs is attractive because of its reduced total parasitic capacitance. This letter reports a comprehensive RF characterization of diodes for RF ESD protection, including S-parameters, parasitic capacitance, and resistance. It is found that a two- or three-diode string may be an optimal RF ESD protection solution due to the balanced overall performance, including ESD protection level, total size, and ESD-induced parasitic effects, etc. An optimized two-diode string for 5 kV ESD protection features a 108.5 fF parasitic capacitance at 2.4 GHz, and is 3680 /spl mu/m/sup 2/ in size. The design was implemented in a commercial 0.35-/spl mu/m BiCMOS technology.

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD+PA performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ~ 18%, all favorable in the same design category.

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractors efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.

On-Chip Integrated Inductors with Ferrite Thin-films for RF IC

This paper reports fabrication of on-chip RF integrated inductors with spin-coated ferrite thin-films (Ni-Zn-Cu-Fe-O, Y-Bi-Fe-O and Co-Zr-O) and high-frequency characterization using equivalent circuit model. Measurement results show that, compared with air-cored inductor, the inductance (L) of Y-Bi-Fe-O and Co-Zr-O thin-film samples increases by 26-50% and 20-39% in 0.1-9GHz, respectively; while the quality factor (Q) of Co-Zr-O inductor is improved by 25-59%. This work demonstrates that the ferrite thin-films are promising for making high-performance integrated compact inductors for RF IC applications

Mixed-mode ESD protection circuit simulation-design methodology

The trial-and-error approach still dominates on-chip electrostatic discharge (ESD) protection circuit design. We present a new predictive mixed-mode ESD protection simulation-design methodology, which involves multiple-level electro-thermal-process-device-circuit-layout coupling in an ESD protection simulation that solves complex electro-thermal equations self-consistently at process, device and circuit levels, in a coupled fashion. In this way, we can investigate ESD protection circuit behavior without any pre-assumption. Practical design examples in commercial 0.35 /spl mu/m CMOS are presented.

A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35 /spl mu/m SiGe BiCMOS

A 5-6 GHz sub-harmonic mixer for a dual-band direct-down conversion transceiver is presented. The sub-harmonic technique is used to alleviate the self-mixing problem of the zero-IF architecture, which deteriorates the system sensitivity by generating a dynamic DC offset. The mixer adopts a single balanced topology that provides easy connection with single-ended LNA and ensures lower power consumption. Both differential output and single-ended output configuration are used. The design is implemented in a commercial 0.35 /spl mu/m SiGe BiCMOS process and features a differential conversion gain of 0 dB at 50 /spl Omega/ load and 15 dB for high-Z load, an IIP/sub 3/ of +2.7 dBm, and a power consumption of 3.7 mA with 3 V supplies.

Ferrite-Partially-Filled on-Chip RF Inductor Fabricated Using Low-Temperature Nano-Powder-Mixed-Photoresist Filling Technique for Standard CMOS

This paper reports new fully-CMOS-compatible on-chip RF inductors with Ni-Zn-Cu and Co2Z-type ferrite-partially-filled structures fabricated using a novel low-temperature nano-powder- mixed-photoresist filling technique. Measured improvements are up to +35% in L and +250% in Q across multi-GHz with f0 to 11.4 GHz.