Haralampos Pozidis

Probe-based ultrahigh-density storage technology

Ultrahigh storage densities can be achieved by using a thermomechanical scanning-probe-based data-storage approach to write, read back, and erase data in very thin polymer films. High data rates are achieved by parallel operation of large two-dimensional arrays of cantilevers that can be batch fabricated by silicon-surface micromachining techniques. The very high precision required to navigate the storage medium relative to the array of probes is achieved by microelectromechanical system (MEMS)- based x and y actuators. The ultrahigh storage densities offered by probe-storage devices pose a significant challenge in terms of both control design for nanoscale positioning and read-channel design for reliable signal detection. Moreover, the high parallelism necessitates new dataflow architectures to ensure high performance and reliability of the system. In this paper, we present a small-scale prototype system of a storage device that we built based on scanning-probe technology. Experimental results of multiple sectors, recorded using multiple levers at 840 Gb/in2 and read back without errors, demonstrate the functionality of the prototype system. This is the first time a scanning-probe recording technology has reached this level of technical maturity, demonstrating the joint operation of all building blocks of a storage device.

Control of MEMS-Based Scanning-Probe Data-Storage Devices

Micro-electro-mechanical-system (MEMS)-based scanning-probe data-storage devices are emerging as potential ultra-high-density, low-access-time, and low-power alternative to conventional data storage. Nanoscale accuracy and short latency in the navigation of the probes are the primary control challenges in probe-storage applications. This paper focuses on the control design to address these challenges in a probe-based storage prototype using a micro-scanner as the nanopositioner for the storage medium. Experimental results demonstrate remarkably short seek times on the order of 1 ms for the worst-case seek operations. Moreover, a thermal-sensor-based approach is compared with a two-sensor-control configuration employing both the global-position information from the thermal sensors and the medium-derived position information. Drift and low-frequency noise can affect the performance of the thermal-sensor-based control scheme over long periods of operation. This is addressed by the second scheme, a novel control architecture based on the Hinfin control framework that uses the best measurement in each of the frequency regions.

Multilevel phase-change memory

Phase-change memory (PCM) has emerged in recent years as one among the most attractive technologies for future non-volatile solid-state memory. PCM relies on the reversible phase transition in chalcogenide materials between different states, i.e., amorphous and poly-crystalline, which are characterized by very different electrical properties. Multilevel storage, namely storage of multiple bits in a memory cell, is a key factor for the competitiveness of PCM technology in the nonvolatile memory market. This paper presents experimental characterization of multilevel PCM devices and addresses the feasibility and reliability issues of multilevel storage using adaptive program-and-verify schemes.

Programming algorithms for multilevel phase-change memory

Phase-change memory (PCM) has emerged as one among the most promising technologies for next-generation nonvolatile solid-state memory. Multilevel storage, namely storage of non-binary information in a memory cell, is a key factor for reducing the total cost-per-bit and thus increasing the competitiveness of PCM technology in the nonvolatile memory market. In this paper, we present a family of advanced programming schemes for multilevel storage in PCM. The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energy-per-bit and cell storage capacity. Experimental results from PCM test-arrays are presented to validate the proposed programming schemes. In addition, the reliability issues of multilevel PCM in terms of resistance drift and read noise are discussed.

Recent Progress in Phase-Change Memory Technology

We survey progress in the PCM field over the past five years, ranging from large-scale PCM demonstrations to materials improvements for high-temperature retention and faster switching. Both materials and new cell designs that support lower-power switching are discussed, as well as higher reliability for long cycling endurance. Two paths towards higher density are discussed: through 3D integration by the combination of PCM and 3D-capable access devices, and through multiple bits per cell, by understanding and managing resistance drift caused by structural relaxation of the amorphous phase. We also briefly survey work in the nascent field of brain-inspired neuromorphic systems that use PCM to implement non-Von Neumann computing.

Resistance switching at the nanometre scale in amorphous carbon

The electrical transport and resistance switching mechanism in amorphous carbon (a-C) is investigated at the nanoscale. The electrical conduction in a-C thin films is shown to be captured well by a Poole–Frenkel transport model that involves nonisolated traps. Moreover, at high electric fields a field-induced threshold switching phenomenon is observed. The following resistance change is attributed to Joule heating and subsequent localized thermal annealing. We demonstrate that the mechanism is mostly due to clustering of the existing sp2 sites within the sp3 matrix. The electrical conduction behaviour, field-induced switching and Joule-heating-induced rearrangement of atomic order resulting in a resistance change are all reminiscent of conventional phase-change memory materials. This suggests the potential of a-C as a similar nonvolatile memory candidate material.

Non-resistance-based cell-state metric for phase-change memory

In phase-change memory (PCM), low-field electrical resistance is typically used to quantify the programmed cell state. However, this metric has several disadvantages. First, it exhibits temporal drift, which is a significant challenge for realizing multilevel PCM. Moreover, because of cell-geometry effects, this metric saturates after a certain point and thus masks the fact that the amorphous size increases with increasing input power. Finally, the resistance is typically measured as the current for a fixed bias voltage, which adversely affects the signal-to-noise ratio at high resistance values. A new metric for the programmed state in a PCM cell is proposed that has significant advantages over the resistance metric in all these aspects and is more representative of the fundamental programmed entity, which is the amorphous/crystalline phase configuration in the PCM cell. Analytical and experimental results are presented that demonstrate the efficacy of the proposed metric.

Nanoscale phase transformation in Ge2Sb2Te5 using encapsulated scanning probes and retraction force microscopy

Encapsulated conducting probes that can sustain high currents are used to study the nanoscale properties of thin-film stacks comprising of a phase-change chalcogenide, Ge(2)Sb(2)Te(5). Scaling studies on this promising candidate for random-access memory devices had thus far required extensive lithography and nanoscale growth. This seriously hampers rapid materials characterization. This article describes the use of two key techniques, an encapsulated conductive probe and its use in retraction mode, whereby the attractive force between tip and sample is used to maintain electrical contact. The effective transformation of nanoscale dots of amorphous Ge(2)Sb(2)Te(5) into the crystalline state is achieved and the electrical conductivity of the transformed structures is probed. The use of retraction force microscopy in a robust manner is demonstrated by reading the conductivity of the crystalline dots. Both these techniques could enable rapid electrical characterization of nanoscale materials, without extensive nanopatterning, thus reducing material development cycles.

Write strategies for multiterabit per square inch scanned-probe phase-change memories

A mark-length write strategy for multiterabit per square inch scanned-probe memories is described that promises to increase the achievable user density by at least 50%, and potentially up to 100% or more, over conventional approaches. The viability of the write strategy has been demonstrated by experimental scanning probe write/read measurements on phase-change (GeSbTe) media. The advantages offered by adopting mark-length recording are likely to be equally applicable to other forms of scanned probe storage.

Multilevel-Cell Phase-Change Memory: A Viable Technology

In order for any non-volatile memory (NVM) to be considered a viable technology, its reliability should be verified at the array level. In particular, properties such as high endurance and at least moderate data retention are considered essential. Phase-change memory (PCM) is one such NVM technology that possesses highly desirable features and has reached an advanced level of maturity through intensive research and development in the past decade. Multilevel-cell (MLC) capability, i.e., storage of two bits per cell or more, is not only desirable as it reduces the effective cost per storage capacity, but a necessary feature for the competitiveness of PCM against the incumbent technologies, namely DRAM and Flash memory. MLC storage in PCM, however, is seriously challenged by phenomena such as cell variability, intrinsic noise, and resistance drift. We present a collection of advanced circuit-level solutions to the above challenges, and demonstrate the viability of MLC PCM at the array level. Notably, we demonstrate reliable storage and moderate data retention of 2 bits/cell PCM, on a 64 k cell array, at elevated temperatures and after 1 million SET/RESET endurance cycles. Under similar operating conditions, we also show feasibility of 3 bits/cell PCM, for the first time ever.