Harald Neubauer
Fraunhofer Society
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Featured researches published by Harald Neubauer.
Measurement Science and Technology | 2008
W. Magnes; Matthias Oberst; A. Valavanoglou; Hans Hauer; Christian Hagen; I. Jernej; Harald Neubauer; W. Baumjohann; D. Pierce; J. D. Means; Peter Falkner
Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability (< 5 pT °C−1 MFA temperature, < ±0.2 nT within 250 h) are very satisfying and the linear gain drift of 60 ppm °C−1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm2 mg−1.
international conference on signals circuits and systems | 2009
Harish Balasubramaniam; Wjatscheslaw Galjan; Wolfgang H. Krautschneider; Harald Neubauer
A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18µm CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback associated with this DAC is the presence of high parasitic bottom plate capacitances. A concept called the floating voltage shield (FVS) is introduced to reduce the effect of these parasitic capacitances and maximize the effective use of the C2C DAC features. The converter consists of the hybrid DAC, a two stage preamplifier followed by a dynamic latch, switch array and digital circuitry for switching and control. The ADC consumes a maximum power of 630µW at a peak conversion rate of approximately 2MS/s from a 1.8V supply voltage and 40MHz clock. Use of extremely simple and yet robust analog architectures for the comparator make the ADC operation less prone to process variation errors.
international conference on ic design and technology | 2008
José Ángel Díaz-Madrid; Harald Neubauer; Ginés Doménech-Asensi; Ramon Ruiz
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.
international symposium on circuits and systems | 2005
Paula López; Matthias Oberst; Harald Neubauer; Johann Hauer; Diego Cabello
Several layout schemes for MOS transistors have been investigated and compared in terms of speed and layout area. Among them, the so-called closed, donut or doughnut transistors have been characterized, obtaining an analytical expression for the calculation of the equivalent W/L ratio for a general n-side regular polygonal-shape. The comparisons show that with quasi-minimum dimension transistors and L=0.35 /spl mu/m, reductions of up to 81% on the drain area can be achieved with an increase of only a 10% on the total layout area for given W and L. An application improving the switching speed of an output multiplexer is shown.
international conference on electronics, circuits, and systems | 2009
Johannes Uhlig; René Schüffny; Harald Neubauer; Johann Hauer; Joachim Haase
This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.
IEEE International Workshop on Medical Measurement and Applications, 2006. MeMea 2006. | 2006
Robert Dorn; Matthias Völker; Harald Neubauer; Johann Hauer; J. Johansson
This paper describes the design and implementation of an integrated frontend for electrocardiographic (ECG) systems, realized in a 0.35 mum 2P4M CMOS process. The performance is optimized to adhere to the standard IEC60601-2-47, which defines the requirements for safety and essential performance of ambulatory ECG equipment. The system consists of three channels to measure the 3 leads of a Goldberger ECG monitoring scheme, therefore a single ended design structure was chosen to minimize the power consumption. A fourth channel is included for additional measurements. Each of the four channels contains a low power multi-bit sigma-delta modulator and a low power digital filter. Three channels are equipped with a low noise preamplifier. The supply voltage can be varied from 2.4 Volt up to 3.6 Volt. With a total power consumption of less than 2 mW the circuit is designed for battery operated equipment
international conference on advanced semiconductor devices and microsystems | 2008
Beatriz Blanco-Filgueira; Paula López; Diego Cabello; J. Ernst; Harald Neubauer; Johann Hauer
The market for solid-state image sensors has been experiencing an explosive growth in recent years resulting in CMOS sensors rapidly becoming one of the emerging sectors with more projection potential in the semiconductors industry. A CMOS active pixel sensor (APS) with a reverse biased p-n junction photodiode constitutes the structure of more widespread use, and it has been made a viable alternative to CCDs with the advent of deep submicron CMOS technologies and microlenses. Peripheral area of the junction depletion region plays an important role on collecting photocarriers in the vicinity of photodiode limits. In this paper, the peripheral photoresponse of CMOS APS of different dimensions in a deep submicron 0.18iquestm process is studied, paying special attention to the bottom collection.
european solid-state circuits conference | 2003
Jonny Johansson; Harald Neubauer; Hans Hauer
To address the growing field of on-line, out-of-hospital health care a front-end ADC for portable electrocardiographic systems has been designed. The converter is realized as a first-order, 3-bit /spl Sigma//spl Delta/ with an oversampling ratio of 512. Performance is optimized to adhere to the standard IEC60601-2-47, which governs ambulatory ECG equipment. The single ended design achieves a dynamic range of 16 bits for signal offsets up to /spl plusmn/1.25V. Measured power consumption is 60 /spl mu/W with supplies of 2.6V analog and 2.2V digital.
international conference on electronics circuits and systems | 2001
Harald Neubauer; T. Desel; H. Hauer
A low power (6.8 mW) 5 V analog 2.7 V digital 16 bit 200 kS/s charge redistribution self calibrating successive approximation (SA) analog/digital converter (ADC) is presented. The device is implemented in a 0.6 /spl mu/m CMOS technology with 2 mm/sup 2/ active area. This multi purpose ADC macro is intended to be integrated with digital signal processing on ASICs. The SA principle permits input multiplexing and sampling at discrete times.
spanish conference on electron devices | 2009
Beatriz Blanco-Filgueira; Paula López; Diego Cabello; J. Ernst; Harald Neubauer; Johann Hauer
This work studies the importance of the peripheral collection in the overall photoresponse in deep sub-micron CMOS 3T Active Pixel Sensors (APS), focusing on the contribution of the bottom surface of the depletion region. We analyze a semi-analytical expression, inspired by previous works, that models the photoresponse of a set of fabricated pixels with octagonal photodiodes that could be easily extended to different geometries. Device simulation results are used to study the behaviour of these structures with the purpose of using Computer Aided Design (CAD) tools for the next technological nodes researchs.