Hare K. Verma

Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations

Variable data width operation in multi-gigabit transceivers on a programmable logic device

High speed configurable transceiver architecture

Programmable logic cells with Local Connections

Dedicated logic cells employing sequential logic and control logic functions

Programmable logic systems and methods employing configurable floating point units

Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes

System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs

Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections

Network physical layer with embedded multi-standard CRC generator