Adebabay M. Bekele

A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS

This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER <;10-15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes.

A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET

A sampling phase detector (SPD) based PLL is presented. The high gain of this programmable SPD suppresses PLLs in-band noise and controls its bandwidth. Instead of sampling the VCO output directly like sub-sampling PLLs, the output of the frequency divider is sampled. This improves capture range and eases high frequency design while maintaining in-band noise reduction. The design uses a single charge pump based frequency acquisition technique with programmability for robust operation. The PLL is realized in a 16nm FinFET process. The SPD improves the measured inband phase noise from −90.6dBc/Hz to −104.1dBc/Hz at 18GHz with RMS jitter of 164fs when integrated over 10KHz–100MHz, while consuming 29.2mW. 2X frequency range of 9-to-18GHz is demonstrated using two LC VCOs.