Hari Ananthan

FinFET SRAM - device and circuit design considerations

The quasi-planar double-gate FinFET has emerged as one of the most likely successors to the classical planar MOSFET for ultimate scalability. Unlike planar devices, its channel width is in the vertical direction; hence it is possible to increase effective channel width (and hence drive current) per unit planar area by increasing fin-height (SOI thickness). This translates directly to improved performance in interconnect-dominated circuits. In this paper we explore the joint V/sub dd/-fin-height-V/sub t/ design space for a 65 nm FinFET SRAM. We report that 69% taller fins can accommodate 18% (140 mV) lower V/sub dd/ as well as 35 % (70 mV) higher V/sub t/ to deliver iso-performance at 87% lower sub-threshold leakage, 50% lower gate leakage, 25% lower dynamic energy, 13% higher static noise margin and 38% higher critical charge for soft-error immunity.

Technology and circuit design considerations in quasi-planar double-gate SRAM

SRAM is likely to remain the largest, leakiest, and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45-nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to understand how its unique properties can be suitably harnessed. Width-quantization limits SRAM sizing choices, while quasi-planarity allows increased cell current by increasing fin height. Conversely, the latter property can be exploited to increase V/sub t/ and/or decrease V/sub dd/ to achieve exponential leakage savings at constant area and read access time. We explore both approaches to selecting the right combination of device structure, V/sub t/ and V/sub dd/ that achieves maximum stability and minimum leakage over the design space. Increasing V/sub t/ with fin height and body thickness improves stability, decreases variability, and decreases source-drain leakage exponentially. But this necessitates the use of small t/sub ox/ to control short channel effect; this increases gate leakage exponentially. On the other hand, increasing V/sub t/ and decreasing V/sub dd/ allows the use of larger t/sub ox/ to maintain short-channel effect and control gate leakage; however, this worsens stability. Careful co-design of device structure, V/sub t/ and V/sub dd/ is imperative to optimize SRAM metrics.

Double-gate SOI devices for low-power and high-performance applications

Double-gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG devices, quasi-planar SOI FinFETs are easier to manufacture compared to planar double-gate devices. DG devices with independent gates (separate contacts to back and front gates) have recently been developed. DG devices with symmetric and asymmetric gates have also been demonstrated. Such device options have direct implications at the circuit level. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50nm circuits. Independent gate control can be used to merge parallel transistors in noncritical paths. This results in reduction in the effective switching capacitance and hence power dissipation. We show a variety of circuits in logic and memory that can benefit from independent gate operation of DG devices. As examples, we show the benefit of independent gate operation in circuits such as dynamic logic circuits, Schmitt triggers, sense amplifiers, and SRAM cells. In addition to independent gate option, we also investigate the usefulness of asymmetric devices and the impact of width quantization and process variations on circuit design.

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS

This paper examines the effectiveness of larger-than-Vdd forward body bias (FBB) in nanoscale bulk CMOS circuits where Vdd is expected to scale below 0.5V. Equal-to and larger-than Vdd FBB schemes offer unique advantages over conventional FBB such as simple design overhead and reverse body bias capability respectively. Compared to zero body bias, they improve process-variation immunity and achieve 71% and 78% standby leakage savings at iso performance and iso active power at room temperature. We also suggest a novel temperature-adaptive body bias scheme to control active leakage and achieve 22% and 40% active power savings at higher temperatures.

A Compact Physical Model for Yield Under Gate Length and Body Thickness Variations in Nanoscale Double-Gate CMOS

Double-gate (DG) CMOS is projected to replace classical bulk and silicon-on-insulator technologies around the 32-nm node. Predicting the impact of process variations on yield for these devices is necessary at an early stage of the design cycle to enable optimal technology and circuit design choices. This paper presents a compact physical model for DG leakage and threshold voltage distribution due to gate length L and body thickness tsi variations, both for single devices and multiple-device stacks. The model is derived directly from the solution of Poisson and Schrodinger equations and thus captures the effect of unique DG phenomena such as volume inversion and quantum confinement. The model is verified for devices at the end of the scaling roadmap (L=13nm, tsi=3nm), with the yield estimation error less than 3% compared to the Monte Carlo simulation for a 3sigma variation of as much as 20% of the nominal process parameters

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS

Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal technology and circuit design choices. This paper presents a fully physical model for double-gate leakage distribution due to gate length (L) and body thickness (tsi) variations, both for single devices and stacks. The model is derived directly from the solution of Poissons and Schrodingers equations, and thus captures the effect of unique double-gate phenomena such as volume inversion and quantum confinement. It is scalable to L = 13nm and tsi = 3nm, with less than 2% error for 3sigma variation as large as 20% of nominal process parameters

Analysis of drain-to-body band-to-band tunneling in double gate MOSFET

An analytical model is proposed for drain-to-body band-to-band tunneling leakage in nanoscale symmetric and asymmetric double-gate MOS devices. The model is used to analyze the impact of technology and circuit parameters, and suggest ways of minimizing this leakage.

Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET

We show that GP-SOI MOSFETs are optimal for the DBB scheme offering high on-current and low design complexity without having power performance issues related to the forward-biased p-n junction current in bulk CMOS. It is also shown that GP-SOI can deliver the same performance as DG-SOI 90X lower standby leakage by dynamically switching the back-gate bias.

Technology-circuit co-design in width-quantized quasi-planar double-gate SRAM

SRAM is likely to remain the largest, leakiest and most process-sensitive circuit block on chip. FinFET, a width-quantized, quasi-planar, double-gate technology, has emerged as the most likely candidate to replace classical technologies around the 45nm node. This paper studies the impact of FinFET design choices on device and SRAM circuit metrics to understand how its unique properties can be suitably harnessed. Width-quantization limits SRAM sizing choices, while quasi-planarity allows increased cell current by increasing fin height. Conversely, the latter property can be exploited to increase V/sub t/ and/or decrease V/sub dd/ to achieve exponential leakage savings at constant access time. The authors explored both approaches to selecting the right combination of device structure, V/sub t/ and V/sub dd/ that achieves maximum stability and minimum leakage over the design space. Increasing V/sub t/ with fin height and body thickness improves stability, decreases variability and decreases source-drain leakage exponentially. But this necessitates the use of small t/sub ox/ to control short channel effect; this increases gate leakage exponentially. On the other hand, increasing V/sub t/ and decreasing V/sub dd/ allows the use of larger t/sub ox/ to maintain short-channel effect and control gate leakage; however, this worsens stability.