Saibal Mukhopadhyay

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.

A circuit-compatible model of ballistic carbon nanotube field-effect transistors

Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.

Process variation in embedded memories: failure analysis and variation aware architecture

With scaling of device dimensions, microscopic variations in number and location of dopant atoms in the channel region of the device induce increasingly limiting electrical deviations in device characteristics such as threshold voltage. These atomic-level intrinsic fluctuations cannot be eliminated by external control of the manufacturing process and are most pronounced in minimum-geometry transistors commonly used in area-constrained circuits such as SRAM cells. Consequently, a large number of cells in a memory are expected to be faulty due to process variations in sub-50-nm technologies. This paper analyzes SRAM cell failures under process variation and proposes new variation-aware cache architecture suitable for high performance applications. The proposed architecture adaptively resizes the cache to avoid faulty cells, thereby improving yield. This scheme is transparent to processor architecture and has negligible energy and area overhead. Experimental results on a 32 K direct map L1 cache show that the proposed architecture can achieve 93% yield compared to its original 33%. The Simplescalar simulation shows that designing the data and instruction cache using the proposed architecture results in 1.5% and 5.7% average CPU performance loss (over SPEC 2000 benchmarks), respectively, for the chips with maximum number of faulty cells which can be tolerated by our proposed scheme.

Gate leakage reduction for scaled devices using transistor stacking

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

In nanoscale CMOS circuits the random dopant fluctuations (RDF) cause significant threshold voltage (Vt) variations in transistors. In this paper, we propose a semi-analytical estimation methodology to predict the delay distribution [Mean and Standard Deviation (STD)] of logic circuits considering Vt variation in transistors. The proposed method is fast and can be used to predict delay distribution in nanoscale CMOS technologies both at the circuit and the device design phase. The method is applied to predict the delay distributions in different logic gates and flip-flops and is verified with detail Monte Carlo simulations. It is observed that a 30% spread (STD/Mean) in Vt variation results in 5% spread in the delay of logic gates (inverter, NAND, etc.). The effect of Vt variation due to RDF is more significant in the setup time (STD/Mean = 11%) and clock-to-output delay (STD/Mean = 5% to 25%) of flip-flops.

Statistical design and optimization of SRAM cell for yield enhancement

We have analyzed and modeled the failure probabilities of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip based on the cell failure probability is proposed. The developed method is used in an early stage of a design cycle to minimize memory failure probability by statistically sizing of SRAM cell.

Leakage Power Analysis and Reduction for Nanoscale Circuits

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems

Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation

In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.