Hari Giduturi | Researchain

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Featured researches published by Hari Giduturi.

international solid-state circuits conference | 2005

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

Mase J. Taub; Rupinder Bains; Gerald Barkley; Hernan A. Castro; Gregory V. Christensen; Sean S. Eilert; Rich Fackenthal; Hari Giduturi; Matthew Goldman; Chris Haid; Rezaul Haque; Krishna Parat; Steve Peterson; A. Proescholdt; Karthi Ramamurthi; Paul D. Ruby; Balaji Sivakumar; Alec W. Smidt; Balaji Srinivasan; Martin Szwarc; Kerry D. Tedrow; Doug Young

A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.

international solid-state circuits conference | 2008

A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Johnny Javanifard; Tris Tanadi; Hari Giduturi; K. Loe; Robert L. Melcher; Shahnam Khabiri; Nicholas T. Hendrickson; A. Proescholdt; David A. Ward; Mark A. Taylor

Advancing to 45 nm 1 Gb NOR flash requires new process and design techniques. The process developments of SACS, tungsten source rail, and better pump capacitors increase cell size and reduce overall die size. The design techniques of two-transistor row decoders, a new sensing architecture, more effective charge pumps and program performance improvements enable multilevel flash cells to meet a die size of 30 mm2 and 5 MB/s program speed in 45 nm technology.

Archive | 2004