Kerry D. Tedrow

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.

Design of a flash-based reference voltage generator for drain bias circuit

The design of a flash-based reference voltage generator used to generate the drain bias reference voltage for flash sensing is described. The flash cell drain must maintain a stable voltage during read operation, irrespective of supply voltage within the chip, to avoid drain disturb condition. Since this reference voltage needs to supply the entire chip, the high capacitance associated with this node usually requires a long time to power-up. A scheme used to reduce the power-up time by a factor 20× from conventional design, while maintaining the design required precision of 2% in the reference voltage output is described. Since the circuit is also required to be ON during the entire operational phase of the chip, design methods used to lower the current consumed by the circuit using a sample-and-hold scheme are also discussed.