Harikrishnan Ramiah

Variable-Order Ant System for VLSI multiobjective floorplanning

Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same search space and time complexity as Corner Sequence (CS), comparatively, CL has more corners to be selected. This compensates the sequence weakness, where modules can be placed freely onto the corners, which are not bounded by the floorplan contour. Two groups of ants, namely VOAS and reconnaissance ants, which will collaborate with each other to determine the local information, are introduced. Through this cooperation, VOAS ant can ascertain its local information greedily, based on the local search space information carried out by reconnaissance ants. Subsequently, VOAS ant proposes a new variable-order property to prioritize the global and local explorations. The variable-order property enables the ants in VOAS to weigh a better choice of modules for the floorplanning, based on the local and global information. The update rules of VOAS are modified in order to handle two-dimensional problem, such as VLSI floorplanning. VOAS shows improved results in terms of purely area optimization as well as composite function of area and wirelength, as compared to other state-of-the-art and recent floorplanning/placement algorithms based on Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) benchmarks.

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

In this paper, a highly efficient and fast transient output capacitor-free low-dropout regulator (LDO) presented. The proposed LDO architecture is based on differential transconductance amplifiers pairing with push-pull stage to enable effective output driving capability. The slew rate at the gate of the output transistor ( SR G ) is further enhanced by common mode-feedback (CMFB) resistors and a coupling capacitor to bypass band-limited components. By adopting adaptive biasing (ADB) technique, the loop bandwidth is extended proportionally to the output load while maintaining high current efficiency at minimum load. The proposed LDO is designed using cost-effective 0.35?m CMOS technology. Post-layout simulation results show that the LDO occupies an active area of 0.069mm2, consuming only a quiescent current of 4.45?A at a minimum load of 100?A. The LDO is able to regulate the output at constant 1.2V with a dropout voltage of 0.2V. When the load is ramped from 100?A to 100mA in 100ns, the output transient can be fully recovered within 2?s. Display Omitted Mathematical formulations are derived to aid in the circuit design.The transient response of the LDO is enhanced by a pair of CMFB resistors.The LDO is able to settle within 2 ?s while consuming 4.45 ?A of quiescent current.

Power Amplifier Design Methodologies for Next Generation Wireless Communications

ABSTRACT As wireless communication standard continues to evolve accommodating the demand of high data rate operation, the design of radio frequency (RF) power amplifier (PA) becomes ever challenging. PAs are required to operate more efficiently while maintaining stringent linearity requirement. In this paper, the design concepts of the PA in addressing these challenges are reviewed. The concepts are divided into two main categories, namely the linearization technique and efficiency enhancement technique. The mandatory attempt in realizing a low-cost design is also discussed.

Hierarchical congregated ant system for bottom-up VLSI placements

A new perturbation method, called Hierarchical-Congregated Ant System (H-CAS) has been proposed to perform the variable-order bottom-up placement for VLSI. H-CAS exploits the concept of ant colonies, where each ant will generate the perturbation based on differences in dimensions of the VLSI modules in hard modules floorplanning and differences in area of the VLSI modules in soft modules floorplanning. In this paper, it is mathematically proved that the area-based two-dimensional cost function for hard modules floorplanning problem can be reduced to the difference-based one dimensional cost function which avoids local optima problems. Lack of global view is a major drawback in the conventional bottom-up hierarchy, and hence, ants in the H-CAS are made to introduce global information at every level of bottom-up hierarchy. A new relative whitespace formula for bottom-up hierarchy is derived mathematically and the H-CAS embeds it in its unique update formula. The ants in H-CAS are able to communicate among themselves and update the pheromone trails when they reach the destination. Then, the ants will congregate, share their experiences and construct a new pheromone trails that belong to this newly constructed group. The congregation of at least two ants and/or ant consortiums would lead to reduction in subsequent search space and complexity. H-CAS gives the best-so-far near optimal solutions and yields low standard deviations of areas involving 9-600 blocks based on Microelectronics Center of North Carolina (MCNC) and Giga scale Systems Research Center (GSRC) benchmarks. The results obtained establish that H-CAS is a high performance placer in respect of scaling, convergence, precision, stability, and reliability. The above claims are based on the comparisons with the other floorplanning algorithms as depicted graphically.

Design of Low-phase Noise, Low-power Ring Oscillator for OC-48 Application

Abstract A low-power, low-phase noise, high tuning range, and fully integrated inductorless RC-VCO (voltage-controlled oscillator) for OC-48 application is designed and simulated in standard 0.18 μm CMOS technology. The proposed inductorless RC-VCO has a simulated phase noise of −141 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz, with a bias current of 605 μA and voltage headroom of 1.8 V. It has 50% tuning range at 2.4 GHz of operating frequency and consumes 1.09 mW of power. This RC-VCO shows a figure of merit performance of −208.2 dBc/Hz at the desired frequency.

Design of ultra-low voltage 0.5V CMOS current bleeding mixer

This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and integrated inductors to achieve ultra-low voltage headroom operation at 0.5V. This mixer is simulated and verified in 0.13µm standard CMOS technology. The result shows a conversion gain (CG) of 11.84dB, 1dB compression point (P1dB) at -14.36dBm, third-order intercept point (IIP3) of -5dBm and a noise figure (NF) of 15dB and with a power consumption of 930µW.

Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator’s high motion losses due to the possibility of their ‘system-on-chip’ integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design’s applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

Efficient and accurate ray tracing method for indoor radio wave propagation prediction in presence of human body movement

Due to the attractive features of millimeter band, its uses are greatly expanding in the indoor wireless communication systems. As the distance between the transmitter and receiver is much shorter in indoor environments than that of the outdoor environments, the radio wave paths of the millimeter band frequencies are highly influenced by the building materials as well as by the human movements. Ray tracing is widely used method to characterize the radio wave propagation for the planning and establishment of the indoor wireless network. Precise object modeling for the real environment and computational burden are the two classical problems of the propagation model. Because, large number of rays that travels in a complex and convoluted indoor environment must be traced. Therefore, an accurate and efficient ray tracing method is proposed here, which is based on the surface separation, object address distribution, and surface skipping techniques. The proposed approach considers the effects of human body movement to provide a realistic estimation of the wave propagation. Hence, an approximated human body model is used to simulate the activities of humans, whereas three-dimensional (3-D) cube or cuboids are used for the remaining objects of the simulation environment. To prove the superiority, complexity analysis and detailed comparisons between the proposed and existing methods are presented in this paper. The results obtained will be of great interest for the proposed ray tracing method that involves human motion within the simple and complex indoor environments.

A new electric dipole model for lightning-aircraft electrodynamics

Purpose – As commercial and military aircraft continue to be subject to direct lightning flashes, there is a great need to characterize correctly the electrical currents and electric potential fluctuations on an aircraft to determine alternative design approaches to minimizing the severity of the lightning-aircraft dynamics. Moreover, with the increased severity of thunderstorms due to global warming, the need arises even more to predict and quantify electrical characteristics of the lightning-aircraft electrodynamics, which is normally not measurable, using a reliable electric model of the aircraft. Such a model is advanced here. The paper aims to discuss these issues. Design/methodology/approach – The case considered in this paper is that of an aircraft directly attached to an earth flash lightning channel. The paper develops a new approach to modelling the aircraft using electric dipoles. The model has the power to represent sharp edges such as wings, tail ends and radome for any aircraft with differen...

A 2-

This paper describes the first linear multistage class-J power amplifier (PA) fabricated in a 2- μm InGaP/GaAs HBT process for multi-band long-term evolution (LTE) applications. It includes a three-stage topology composed by a pre-driver, driver, and a class-J main stage, to optimize the output power and power-added efficiency (PAE) over 1.7-2.05 GHz, thus encapsulating the LTE bands 1 to 4, 9 to 10, 33 to 37, and 39. This is achieved through a novel analog pre-distorter linearizer, which features two sub-circuits for AM-AM and AM-PM linearization. The PA prototype meets the standards adjacent channel leakage ratio at a maximum linear output power of 28 dBm. Tested at 2.05 GHz and for a 16-QAM scheme, the maximum error vector magnitude is 3.38% at a 28-dBm output power, which corresponds to a PAE of 40.5%-55.8% across bands. The input return loss is 15 dB and the maximum power gain is 35.8 dB, while demonstrating an unconditional stable characteristic from dc up to 5 GHz. The die area is 950 μm×900 μm. The performance metrics compare favorably with the state-of-the-art.