Tun Zainal Azni Zulkifli

Design, Simulation and Measurement Analysis on the S-parameters of an Inductively-degenerated Common-source Open-drain Cascode Low Noise Amplifier

An inductively-degenerated common-source (CS) open-drain cascode LNA was designed for W-CDMA application. The operating frequency for the design was at 2.14 GHz, which is at the center of the reception range of the W-CDMA standard. The supply voltage is 1.8 V at 0.18 mum CMOS process. The LNA was designed using power-constrained noise optimization method in obtaining the width of the transistor of 290 mum. Post-layout simulations with distributed resistors and capacitors were performed. On-chip inductors with quality factor of 8 were utilized to resonate with the metal-insulator-metal capacitor (mimcap). The mimcap was also used to isolate VDD and ground. The input was 50 Omega matched using the transistor as well as an inductor at the gate and three parallel 1.65 nH inductors acting as a 0.55 nH degeneration inductor at the source. Detailed design steps are described in this paper with plots of the post-layout simulation and measurement results provided. These plots are analyzed extensively in this paper and justification for the errors are given. The 12.8 dB of S21 obtained from the post-layout and a much less 7.8 dB from the measurement shows that there is an offset by 5 dB. Derivations are given to show that the unmatched output is the cause of the gain offset. S11 is measured at -24 dB which is very close to the simulated value of -25.4 dB. The current measured and simulated at a bias voltage of 0.65 V is 4.1 mA.

A reconfigurable LNA for multi-standard receiver using 0.18 μm CMOS technology

This paper presents the design of a reconfigurable low noise amplifier (LNA) for multi-standard multi-band receiver. In this design, inductively-degenerated common-source (IDCS) topology is chosen as it has been proven to be a good choice in designing multi-standard multi-band LNA. The design is using 0.18 μm CMOS technology. The reconfigurable LNA has been designed to operate in two bands of standards consisting the bands range from 800 to 1000-MHz (lower band) and 1800 to 2200-MHz (upper band). The simulation results exhibit gain S21 of 12.9-dB for lower band and 12.4-dB for upper band, input reflection S11 of −14.5-dB and −17.2-dB for both bands, and output return loss S22 of −14.7-dB and −26-dB for lower and upper band making the LNA suitable for most of the mobile communication applications. The LNA also exhibits the noise of figure of 2.55-dB and 2.3-dB for lower and upper band respectively. The circuit consumes 26.5 mW when operating in lower band mode and uses 18.8 mW of power when operating in upper band mode.

Systematic Width Determination for the Design of Power-Constrained Noise Optimization Inductively Degenerated Low Noise Amplifier

Abstract Systematic width determination for the inductively degenerated low noise amplifier (IDLNA) was implemented using power-constrained noise optimization (PCNO) technique. Using drain current for short channel equation, the power dissipated (PD) as a function of gate overdrive (VOV) expression was derived. This expression was further arranged to represent PD as a function of input stage quality factor (QS). The two relations were translated into contours which were generated at fixed noise figure (NF). By means of manipulating the same equations, the NF as a function of QS was derived. The contours were generated using the parameters specified for Silterra’s 0.18 μm CMOS process for Wideband-Code Division Multiple Access (W-CDMA) application. The PD versus VOV contours show that the NF of the LNA can be improved if PDis increased. These contours also illustrate that for a W-CDMA with a requirement of below 2.5 dB of NF, the VOVis in the range of 46–115 mV. The PD and NF versus QS contours show that minimum PD for each NF and minimum NF at each PD is maintained at QS equal to 4, independent of the process and operating frequency. This result is verified by derivations and comparisons with a referenced article. With the optimum QS known, the calculated transistor’s width is 330 μm to provide an NF of 1 dB at 6 mW of power.

0.18 µm fully integrated 900 MHz CMOS LNA with input and output on-chip matching for multi-standard mobile receiver

This paper presents a fully integrated single-ended low noise amplifier (LNA) for GSM (GSM850 and GSM900) and UMTS (UMTS Band V and VI). The design and implementation is based on inductively-degenerated common-source (IDCS) using 0.18 μm CMOS technology with on-chip inductors at the input circuit for input matching and extra on-chip RL components at load tank for output matching. Post layout simulation results shows a power gain of 10.07-dB, a noise figure of 2.4-dB and an input and output return losses well below -10-dB at the center frequency of 900-MHz. The current consumption for this circuit is 7.1-mA from a voltage supply of 1.8-V.

Fully integrated 2-GHz LNA with on-chip matching for multi-standard mobile receiver using 0.18 μm CMOS technology

A single-ended wideband low noise amplifier (LNA) for GSM (DCS1800, PCS1900) and WCDMA (Band I to IV) were designed and implemented using 0.18 mum CMOS technology. The circuit topology is based on inductively-degenerated common-source (IDCS) using on-chip inductors at the input circuit for input matching and shunt-peaking components for bandwidth enhancement at load tank. Post layout simulation results shows a power gain of 24-dB, a noise figure of 2.26-dB and an input return loss well below -10-dB at the center frequency of 2-GHz. The LNA draws 6.8-mA from a single 1.8-V power supply.

A 1.4dB Noise Figure CMOS LNA for W-CDMA Application

This paper presents a 2.14 GHz low noise amplifier (LNA) intended for use in a wide-band code division multiple access (W-CDMA) receiver. The LNA has been implemented in RF 0.18mum CMOS process. The amplifier provides a forward gain (S21) of 11dB with a noise figure of only 1.4dB from a 1.8V supply voltage. The input power 1dB-compression point of the LNA is -11dBm and the input referred 3rd-order intercept point is 6.6dBm. Total power consumption is 23mW as current consumed by the circuit is 12.7mA. The LNA is differential in nature and is of the inductive source degeneration type. In this paper, detailed analysis of the LNA architecture is presented

Design and Simulation of RF-CMOS Spiral Inductors for ISM Band RFID Reader Circuits

The recent popularity of RFID tags has generated research for accompanying miniature, low-power reader circuits. This work illustrates the design of RF complementary metal- oxide-semiconductor (CMOS) process compatible spiral inductors. Several simulators such as AWR Microwave Officereg, SONNETreg, and finite element program CST were used to provide its S21 and S31 transmission characteristics, approximate and finalized design layout values respectively. This design utilized Silterra 0.18 mum RF-CMOS technology process parameters. Simulation results indicate that inductors core diameters must be adequately large (more than 100 mum) to ensure high quality factor characteristics and its conductor spacing should be minimal to obtain larger per unit area inductive value. The proposed design methodology optimizes the conductor width of inductors to allow alignment of the peak quality factor with the circuits operating frequency, thereby enhancing the input/output matching characteristics and S-parameter extraction in the GHz region.

A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application

In this paper, a fully balanced 10-Gb/s differential output transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology for SDH/SONET application. The TIApsilas input dynamic range is further improved by adding an automatic gain control (AGC) amplifier circuit. To extend the -3-dB bandwidth in a limited 0.18-mum CMOS process, this design utilizes the series peaking technique with 50-Omega output buffer while achieves the differential gain of 62-dBOmega and the bandwidth of 8.1-GHz in the presence of 0.2-pF photodiode capacitance. This TIA operates from a dual supply voltages of 1.8-V for TIA core and 2.2-V for the AGC block while consuming 70-mW of total chip power with the input sensitivity of -15-dBm for a bit error ratio (BER) of 10-12.

A general on-wafer noise figure de-embedding technique with gain uncertainty analysis

This paper reports a general on-wafer noise figure (NF) de-embedding technique with the analysis of two gain definitions. As implemented in this work, all elements involved in NF measurement were determined and classified as a multi-stage network, and the well-known Friis law is applied to correct the noise contributions coming from other stages. With the two gain definitions, the effects of impedance match on NF are investigated. The result shows an NF of 3.80dB obtained with the de-embedding method and 6.06dB without the de-embedding method. This result is for vector measurement using the available gain, which gives 0.18dB improvement in NF as opposed to scalar measurement utilizing the insertion gain. Furthermore, NF was also measured at 5.63dB, 5.76dB, and 4.75dB under three different source impedances, namely, short, open, and load, respectively.

A 24mW, 5Gb/s fully balanced differential output trans-impedance amplifier with active inductor and capacitive degeneration techniques in 0.18µm CMOS technology

In this paper, a low power 24mW 5Gb/s differential output transimpedance amplifier (TIA) is realized in 0.18µm CMOS technology for optical interconnect application. The TIA is a fully balanced and differential architecture design that can improve immunity with the common mode noise attributed to the power supply. The differential gain achieved is 66dBΩ with a -3dB bandwidth of 4.0GHz for a 0.5pF photodiode capacitance (Cpd) by implementing both the active inductor peaking and capacitive degeneration techniques. The TIA core consumes only 24mW power from a single 1.8V power supply while achieving the sensitivity of -19.0dBm for a bit error rate (BER) of 10-12.