Harri Sorokin

Complex-valued QR decomposition implementation for MIMO receivers

Multiple input multiple output (MIMO) transmission is an emerging technique targeted at 3G long term evolution (LTE) systems. One vital baseband function in MIMO receivers is QR decomposition of the channel matrix. In this paper, a processor based complex-valued QR decomposition is presented. The processor is enhanced with complex arithmetic and inverse square root function units. The proposed processor fits well with the real-time requirements of the MIMO receiver. The computing power is tailored for typical MIMO systems. Due to the generality of the applied computing resources it can also be used for other tasks. Also, the presented principles can be applied on any customizable processor architectures to accelerate QR decomposition.

Conflict-free parallel memory access scheme for FFT processors

In this paper, a parallel access scheme for constant geometry FFT algorithms is proposed, which allows conflict-free access of operands distributed over parallel memory modules. The scheme is a linear transformation and the address generation is performed with the aid of bit-wise XOR operations. Different FFT lengths can be supported with the aid of a simple address rotation unit. The scheme is general supporting several radices in FFT computations and different numbers of parallel memory modules. The scheme allows parallel butterfly computations independent of the FFT length.

A Programmable Max-Log-MAP Turbo Decoder Implementation

In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.

Stride permutation networks for array processors

In several digital signal processing algorithms, the computation is performed in consecutive stages consisting of parallel computational nodes. The stages are decoupled by data permutations where stride permutations are common because of their regularity. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, register-based stride permutation networks are proposed for array processors where the storage requirement of the networks is relatively small, and thus, memory-based structures would be an expensive solution. The proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Furthermore, the networks are generated without heuristics, which makes them attractive for automated design procedures.

Conflict-free parallel access scheme for mixed-radix FFT supporting I/O permutations

FFT algorithms are inherently highly parallel and often require frequent access to memory indicating need for high memory bandwidth. Unfortunately, in-place FFT algorithms access data in specific data patterns, thus conflict-free parallel access calls for specialized access schemes. In this paper, we propose a conflict-free parallel access scheme for mixed-radix FFT computations, which supports not only the kernel computations but also I/O permutations of the FFT. The scheme supports all the sequence sizes of power-of-two and all the power-of-two numbers of memory modules. The implementation of the address generation unit is simple requiring only XOR gates and hardwiring.

Low-power signal acquisition for galileo satellite navigation system

In satellite navigation systems based on code division multiple access, the signal acquisition in receiver is a computationally intensive task where the received signal is correlated with long pseudo random noise codes. In this paper, a novel architecture for acquisition of signals with binary offset modulation is proposed. The architecture is modular and has low power consumption due to word-parallel correlation structure.

Stride Permutation Networks for Array Processors

In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.

Low-complexity polynomials modulo integer with linearly incremented variable

Computation of a polynomial function modulo integer with linearly incremented variable is required by certain number generators like, e.g., an interleaver of the turbo decoder in telecommunication field. In this paper, a systematic method for deriving hardware structures for such computation is proposed. The method is derived by recursively applying principles of simplifying modulo operations in a limited domain. With the aid of the proposed method, efficient hardware structures can be derived for any polynomials and significant savings can be obtained in the hardware complexity when compared to the straightforward modulo arithmetic. As a case study, the method is applied on the 3G long term evolution (LTE) interleaver.

Coding method for embedding audio in video stream

In this paper, a new method for synchronous coding of digital audio and video signals is proposed. The audio signal is embedded within video signal to produce synchronous hybrid signal that is further encoded. The receiver is able to extract the audio signal from the hybrid signal, and thus, is able to reconstruct two separate signals, the audio and the video. The proposed method enables synchronous coding, transmission, storage, and playback of a video signal and the associated audio signal. The scheme can be used with the current and the developing coding standards to enable the accurate synchronization for the audio and the video data.

Operand access in regular topology discrete trigonometric transforms

In this paper, we consider operand access in fast algorithms for discrete trigonometric transforms having topology based on stride permutations.We show how the operand access in such algorithms can be performed with simple bit manipulations, which provides savings in application-specific implementations. In addition, 2-dimensional transforms are considered and we show that the same simple operand access methods are applicable.