Harry F. Jordan

Serial array time slot interchangers and optical implementations

We consider time slot interchangers (TSIs) which are built from 2/spl times/2 exchange switches and delays and which are useful for time division multiplexed (TDM) systems in telecommunications and pipelined systems such as time multiplexed optical multiprocessors. We formulate a general method for constructing TSIs based on multistage interconnection networks in the space domain via space-to-time mapping. Two types of TSIs, time slot permuters and time slot sorters, are considered. We review the time slot permuter based on the Benes network, and obtain the /spl Lambdaspl tilde/ time slot permuter based on the bit-controlled, self-routing /spl Lambda/ permutation network. The time slot sorter, S/sub N/, is obtained from the Batcher spatial sorting network. The generalized Lambda time slot permuter /spl Lambdasub Nsup q/ is obtained, in an algorithmic approach, by combining the idea of the /spl Lambdaspl tilde/ time slot permuter and Q-way bitonic decomposition (Q=2/sup q/). The numbers of switches, control complexities, and frame delays of these architectures are compared, and the problem of crosstalk in optical implementation is discussed. It is shown that control complexity can be traded against the number of switches. >

Bit-serial architecture for optical computing

The design of a complete, stored-program digital optical computer is described. A fully functional, proof-of-principle prototype can be achieved by using LiNbO(3) directional couplers as logic elements and fiber-optic delay lines as memory elements. The key design issues are computation in a realm where propagation delays are much greater than logic delays and implementation of circuits without fip-flops. The techniques developed to address these issues yield architectures that do not change as their clocking speed is scaled upward and the size is scaled downward proportionally; these are called speed-scalable architectures. Signal amplitude restoration and resynchronization are accomplished by the novel technique of switching in a fresh copy of the system clock. Device characteristics that are important to the proof-of-principle demonstration are discussed, including the special properties and limitations that are important when designing with them. Design principles are exemplified by the design of an n-bit counter. Following this, the design for a stored-program bit-serial computer is described. We estimate that the described prototype architecture can be operated in the 100-MHz region with off-the-shelf components, and in the O. 1-1-THz region with foreseeable future components.

Performance measurements on HEP - a pipelined MIMD computer

A pipelined implementation of MIMD operation is embodied in the HEP computer. This architectural concept should be carefully evaluated now that such a computer is available commercially. This paper studies the degree of utilization of pipelines in the MIMD environment. A detailed analysis of two extreme cases indicates that pipeline utilization is quite high. Although no direct comparisons are made with other computers, the low pipeline idle time in this machine indicates that this architectural technique may be more beneficial in an MIMD machine than in either SISD or SIMD machines.

Comparing barrier algorithms

Abstract A barrier is a method for synchronizing a large number of concurrent computer processes. After consideration of some basic synchronization mechanisms, a collection of barrier algorithms with either linear or logarithmic depth will be presented. A graphical model is described that profiles the execution of the barriers and other parallel programming constructs. This model shows that in order to achieve the best performance, different situations call for different barrier implementations. Timing experiments supporting these conclusions are detailed.

Structuring parallel algorithms in an MIMD, shared memory environment

Abstract This paper discusses the class of algorithms having global parallelism, i.e. those in which parallelism is introduced at the top of the program structure hierarchy. Such algorithms have performance advantages in a shared-memory. MIMD computational model. A programming environment consisting of FORTRAN, enhanced by some pre-processed macros, has been built to aid in writing programs for such algorithms for the Denelcor HEP multiprocessor. Applications of from tens to hundreds of FORTRAN statements have been written and tested in this environment. A few parallelism constructs suffice to yield understandable programs with a high degree of parallelism. The automatic generation of programs with global parallelism seems to be a promising possibility.

Fiber optic delay line memory

A model for digital synchronous delay line memory (DSDLM) is given, yielding limitations on the maximum number of bits that can be reliably stored for a given change in delay medium temperature and amount of medium dispersion. More than 22 million bits can be stored when single-mode optical fiber is used as the medium, but only if operated at the wavelength of minimum dispersion and by limiting thermal fluctuations to within 0.002 degrees C. A DSDLM is being constructed using such fiber, along with lithium niobate directional couplers as the switching elements. Signal regeneration errors, switch crosstalk, and polarization losses are negligible for the implementation. With a modulation frequency of 100 MHz, a single-line 2000-bit memory can be reliably operated without thermal compensation given a temperature fluctuation of <80 degrees C.

Experience with pipelined multiple instruction streams

Pipelining has been used to implement efficient, high-speed vector computers. It is also an effective method for implementing multiprocessors. The Heterogeneous Element Processor (HEP) built by Denelcor Incorporated is the first commercially available computer system to use pipelining to implement multiple processes. This paper introduces the architecture and programming environment of the HEP and surveys a range of scientific applications programs for which parallel versions have been produced, tested, and analyzed on this computer. In all cases, the ideal of one instruction completion every pipeline step time is closely approached. Speed limitations in the parallel programs are more often a result of the extra code necessary to ensure synchronization than of actual synchronization lockout at execution time. The pipelined multiple instruction stream architecture is shown to cover a wide range of applications with good utilization of the parallel hardware.

Digital optical computing with optically switched directional couplers

Optically switchable directional couplers can function as logically complete building blocks for constructing all-optical computational engines. Logically, such devices operate as all-optical five-terminal gates, where the two output signals are logical functions of two throughgoing input signals and a control input signal. Such an optically controlled exchange element is a promising functional unit for constructing general-purpose digital optical logic circuits. The implementation of such all-optical five-terminal gates using Ti:LiNbO3 electro-optic directional couplers is described. These optical logic gates utilize mature technology developed for the telecommunications industry, facilitating construction of robust optical logic hardware. Single-mode optical fiber is used for all logical interconnections. Effectively dc-coupled control circuitry converts optical pulses into electrical pulses capable of switching the transfer state of low-voltage lumped electrode directional couplers. The use of such Ti:LiNbO3 five-terminal optical logical gates in the construction of various simple circuits such as oscillators and divide-by-N circuits is shown. Such circuits demonstrate many of the issues arising in the construction of all- optical digital computing systems, and are fundamental subsections of an all-optical bit serial computer design currently under construction.

Optoelectronic time-of-flight design and the demonstration of an all-optical, stored program, digital computer

The recent demonstration of an all-optical, stored-program, digital computer by our group focused on high-speed optoelectronic design. It was made possible by a new digital design method known as time-of-flight design. A rudimentary, but general-purpose, proof of principle computer was built, which is all-optical in the sense that all signals connecting logic gates and all memory are optical in nature. LiNbO/sub 3/ directional couplers, electrooptic switches, are used to perform logic operations. In addition to demonstrating stored program operation in an optoelectronic digital computer, the system demonstrated the feasibility of the new design method, which does nor use any flip-flops or other bistable devices for synchronization or memory. This potentially allows system clock rates of the same order as device bandwidth. This paper describes how the time-of-flight design method was motivated by the special properties of optoelectronic digital design. The basic principles of the method we employed will be discussed along with some of its potential advantages. The experimental work with digital optical circuits leading up to and including the stored program computer experiment will then be discussed. Finally, the future potential of time-of-flight design in high-bandwidth optoelectronic systems will be discussed. >

Report of the Purdue Workshop on Grand Challenges in Computer Architecture! for the Support of High Performance Computing

Abstract The “Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing” was sponsored by the National Science Foundation to identify critical research topics in computer architecture as they relate to high performance computing. Following a wide-ranging discussion of the computational characteristics and requirements of the grand challenge applications, the workshop identified four major computer architecture grand challenges as crucial to advancing the state of the art of high performance computation in the coming decade. These are: (1) idealized parallel computer models; (2) usable peta-ops (1015 ops) performance; (3) computers in an era of HDTV, gigabyte networks, and visualization; and (4) infrastructure for prototyping architectures. This report overviews some of the demands of the grand challenge applications and presents the above four grand challenges for computer architecture.