Kyungsook Y. Lee

On the Rearrangeability of 2(Iog 2 N) –1 Stage Permutation Networks

For any parallel computer systems which consist of many processing elements and memories, interconnection networks provide communication paths among processing elements and memories. Both the rearrangeability proof and the control algorithm are well known for the Benes network, which is intrinsically symmetric. However, there has been little progress for the case of nonsymmetric networks of similar hardware requirements.

A New Benes Network Control Algorithm

A new Benes network control algorithm is presented. Unlike the original looping algorithm, the new algorithm is not recursive. In this algorithm (N x N) Benes network is viewed as a concatenation of two subnetworks SN1 and SN2. The first (log N - 1) stages of a Benes network correspond to SN1, and the remaining log N stages correspond to SN2. SN1 is controlled by a full binary tree of set partitioning functions, called a Complete Residue Partition Tree, and SN2 is bit controlled. The new control algorithm sets switches one stage at a time, stage by stage.

The knockout switch under nonuniform traffic

The knockout switch is a nonblocking, high-performance switch suitable for broadband packet switching. It allows packet losses, but the probability of a packet loss can be kept extremely small in a cost-effective way. The performance of the knockout switch was analyzed under uniform traffic. In this paper, we present a new, more general analytic model of the knockout switch, which enables us to evaluate the knockout switch under nonuniform traffic. The new model also incorporates the effects of a concentrator and a shared buffer on the packet loss probability. Numerical results for nonuniform traffic patterns of interest are presented. >

Serial array time slot interchangers and optical implementations

We consider time slot interchangers (TSIs) which are built from 2/spl times/2 exchange switches and delays and which are useful for time division multiplexed (TDM) systems in telecommunications and pipelined systems such as time multiplexed optical multiprocessors. We formulate a general method for constructing TSIs based on multistage interconnection networks in the space domain via space-to-time mapping. Two types of TSIs, time slot permuters and time slot sorters, are considered. We review the time slot permuter based on the Benes network, and obtain the /spl Lambdaspl tilde/ time slot permuter based on the bit-controlled, self-routing /spl Lambda/ permutation network. The time slot sorter, S/sub N/, is obtained from the Batcher spatial sorting network. The generalized Lambda time slot permuter /spl Lambdasub Nsup q/ is obtained, in an algorithmic approach, by combining the idea of the /spl Lambdaspl tilde/ time slot permuter and Q-way bitonic decomposition (Q=2/sup q/). The numbers of switches, control complexities, and frame delays of these architectures are compared, and the problem of crosstalk in optical implementation is discussed. It is shown that control complexity can be traded against the number of switches. >

The B-network: a multistage interconnection network with backward links

A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2*2) switches, while having the same hardware complexity as the gamma network. >

The extra stage Gamma network

The augmented data manipulator (ADM), inverse augmented data manipulator (IADM), and the gamma network are based on the Plus-Minus-2i connection patterns. In such a network there exist multiple paths to connect a source S to a destination D except when S=D. The number of paths for (S,D) is a function of the tag value (D-S) modulo N, and the size of the network N. par>It is shown in this paper that by adding an extra stage to the original PM21 interconnection network, multiple paths are provided for all the tag value including 0. The extra stage can be any stage out of n=log2N stages of the original network. The analyses on the distribution of the number of paths for various tag values are performed for n possible choices of the extra stage. It is shown that the extra stage of 0, +1, -1 connection patterns gives the most uniform distribution, and also results in a 1-fault tolerant interconnection network.

KSMINs: knockout switch-based multistage interconnection networks for high-speed packet switching

We propose knockout switch-based multistage interconnection networks (KSMINs) for fast packet switching, combining the well-known knockout switch and the concept of multistage interconnection networks. The main objective is to reduce the severe pin requirements of large knockout switches through a phased address filtering. We present an approximate Markov-chain model of KSMINs to study the performance of KSMINs with different numbers of address-filtering phases. The model is shown to be accurate within 5% for all the cases considered and within 20% for the meaningful cases of the buffer sizes /spl ges/4. For the (256/spl times/256) KSMIN, two-phase address filtering based on the (16/spl times/16) knockout switches is shown to perform very closely to the single-stage knockout switch for a reduced hardware cost. >

KSMINs: knockout switch based multistage interconnection networks for high-speed packet switching

Knockout-switch-based multistage interconnection networks (KSMINs) for fast packet switching, combining the well-known knockout switch and the concept of multistage interconnection networks are proposed. The main objective is to reduce the severe pin requirements of large knockout switches through phased address filtering. An approximate Markov chain model of KSMINs is presented to study the performance of KSMINs with different numbers of address filtering phases. The model is shown to be accurate within 5 % for all the cases considered, and within 2 % for the meaningful cases of the buffer sizes >or=4. For the (256*256) KSMIN, two-phase address filtering based on the (16*16) knockout switches is shown to perform very closely to the single-stage knockout switch for a much-reduced hardware cost.<<ETX>>

The PM221 interconnection network

A scheme based on the standard multiplier recoding technique that enables the use of (5*5) switches for PM2I networks is presented. The connections between switching stages are based on the modified PM2I functions, and are called plus-minus-2/sup 2i/ (PM22I); hence, these networks are called the PM22I networks. Since the number of switching stages in the PM22I networks is one-half of those in the PM2I networks, with a moderate increase in the switch size from (3*3) to (5*5), these networks provide similar design tradeoffs availability by the (2*2) and (4*4) cube networks. >

Optical TDM sorting networks for high-speed switching

The general time-space-time switching problem in telecommunications requires the use of multichannel time slot interchangers. We propose two multichannel time slot sorters which sort N/sup 2/ time-division multiplexed (TDM) optical inputs, arranged as N frames with N time slots per frame using O(Nlog/sup 2/N) optical switch elements. The TDM optical inputs are sorted in place without expanding the space-time fabric into a space-division switch. The hardware components used are 2/spl times/2 optical switches (LiNbO/sub 3/ directional couplers) and optical delay lines connected in a feedforward fashion. Two space-time variants of the spatial odd-even merge algorithm are used to design the sorters. By maintaining the number of shift-exchange operations invariant at each stage, the proposed sorters use fewer switches than previously proposed sorters using switches with feedback line delays. The use of local control at each 2/spl times/2 switch makes the proposed sorters more practical for high-speed optical inputs than Benes-based time slot permuters with global control and high latency, which affects interframe distance. Both time slot sorters support pipelining of input frames and sorted outputs are available at each time slot after an initial frame delay. The proposed sorters find practical application in the time-domain equivalents of space-division, nonblocking, self-routing packet switches using the sort-banyan architecture, such as the Starlite switch, Sunshine switch, etc.