Harry Fujimoto

Thin Film Cracking and Ratcheting Caused by Temperature Cycling

Layered materials are susceptible to failure upon temperature cycling. This paper describes an intriguing mechanism: cracking in a brittle layer caused by ratcheting in an adjacent ductile layer. For example, on a silicon die directly attached to an organic substrate, cracking often occurs in the silicon nitride film over aluminum pads. The silicon die and the organic substrate have different thermal expansion coefficients, inducing shear stresses at the die corners. Aided by cycling temperature, the shear stresses cause ratcheting in the aluminum pads. Incrementally, the stress relaxes in the aluminum pads and builds up in the overlaying silicon nitride film, leading to cracks.

Quantitative Measurement of Interface Fracture Energy in Multi-Layer Thin Film Structures

Interfacial debonding of multi-layer thin film systems can severely affect the reliability of devices. To quantitatively evaluate the interface adhesion strength, a sandwich structure four-point bending technique was developed. In the sandwich structure samples, the thin film structure of interest was diffusion bonded between two silicon substrates. A fourpoint bending method was applied to propagate a crack along the interface of interest. Two thin film systems with nominally the same structure, but processed under different conditions, were measured for their SiO2/TiN interface fracture energies. Results showed that the interface fracture energy of one system was about 50% larger than that of the other system. Cross-section TEM observations revealed that the stronger interface was also significantly rougher.

Developing design rules to avert cracking and debonding in integrated circuit structures

Abstract In an integrated circuit, stresses come from many sources (e.g., differential thermal expansion and electromigration). The circuit structures are never perfect, possibly containing crack-like flaws. The stresses may drive the pre-existing cracks to grow and cause circuit failure. We explore a fracture mechanics approach to formulate design rules to avert crack growth. We adopt a strategy based on two attributes of integrated circuits. First, high tensile sress is generated by internal misfit, and is therefore confined in small regions with size comparable to the feature dimension. Second, the fabrication process is controlled down to the individual features, so that the pre-existing cracks are expected to be smaller than the feature sizes. Instead of considering pre-existing crack, we consider all possible pre-existing cracks, and require that none of them should grow. Such a no-cracking condition is independent of the nature of pre-existing cracks; rather, it depends on parameters that define a circuit structure, such as the feature size and the aspect ratios of the geometry. Furthermore, the stress singularity at sharp corners in a circuit structure does not cause any particular difficulty. We illustrate these ideas with elementary examples involving blanket films and isolated interconnect lines. Then in the spirit of design rules, we investigate a multilevel interconnect test structure to avert channeling cracks caused by differential thermal expansion.

Mechanical behaviour of submicron multilayers submitted to microtensile experiments

Abstract The mechanical strength of layers used in microelectronic circuits is not well understood. In this study in situ microtensile tests were performed in a scanning electron microscope on various multilayers of Al-0.5%Cu, Ti and TiN deposited on a Ti substrate. Film fracture occurred in two distinct modes, either perpendicular to the loading or at a 45° angle to the loading direction. Samples were loaded until the cracked films began to debond from the substrate. By using X-ray diffraction (XRD) and energy dispersive spectroscopy (EDS) the weak interface was determined to be the Al to Ti interface. The strength of this interface was calculated to be 0.5 J/m 2 , which is in good agreement with theoretical predictions.

Micron-sized channel-dropping filters using silicon waveguide devices

High density integrated optics on the scale of VLSI is of interest as it allows complicated optical interconnect circuitry to be mass produced. In this paper we present micron-sized high Q resonant cavity structures based on silicon on insulator devices. These resonant cavities may be used in channel dropping filters and modulators. Because of their small size, they have high packing densities on the order of one million devices per square centimeter. This technology has the added advantage in that it can utilize the embedded VLSI electronics manufacturing capacity. In previous work, we studied silicon on oxide photonic band gap (PBG) devices and demonstrated devices with a 400 nm stop band and with a defect which had a Q of 265 centered at a wavelength of 1560 nm. In addition, we fabricated 3 to 5 micrometer radii micro-rings with Qs of approximately 250 and free spectral widths of over 20 nm. In this work, we report results on micro-racetracks, which are oval shaped resonators, with resonances that are approximately 16 nm apart and Qs of about 1000. These racetracks incorporate a vertical coupling technology in which the bus waveguides and the ring are on separate planes. This vertical coupling scheme allows for independent control of the Q of the ring via the distance between the ring and the bus. We demonstrate higher order multi-resonator filters with similar Q and free spectral range to the single resonator filters. The individual resonators in each filter have slightly different resonant frequencies from each other resulting in multi-peaked resonances and lower drop efficiencies. Finally, we show that it is possible to thermally tune the resonances by 1 nm leading to a 10:1 contrast ratio.

Adhesion Measurement of Interfaces in Multilayer Interconnect Structures

Interface decohesion is increasingly becoming a reliability concern in multilayer interconnect structures. It is therefore necessary to provide adhesion tests as a part of materials characterization procedures and to study the fundamental material properties that affect interface toughness. A sandwich structure 4-point bend test was developed for measuring the adhesion between interlayer dielectric and metal interfaces. This technique offers well defined and easily controllable fracture processes and simple analyses based rigorously on fracture mechanics. Using this technique, a number of interfaces were studied. For conventional interconnect systems consisting of Al lines and SiO 2 as the interlayer dielectric, the focus was to improve the interface fracture toughness through structure design and process engineering. Potential low dielectric constant materials, such as polymers and porous SiO 2 , were also studied as candidates for interlayer dielectric materials in the future. Interface strengthening effects of both mechanical and chemical origin, including interface roughness and thin film plasticity, as well as alteration of chemical bonding were explored.

Subcritical Debonding of Multilayer Interconnect Structures: Temperature and Humidity Effects

Thin film structures may fail by progressive or time-dependent debonding at stresses far below those required for catastrophic failure. Previous work has shown that progressive debonding in a typical interconnect structure occurs either along the TiN/SiO 2 interface or parallel to this interface in the SiO 2 Such subcritical debonding was found to span several orders of magnitude of debond growth rates and occur at significantly reduced driving forces. The presence of SiO 2 at the failure location indicates that the mechanisms which give rise to stress corrosion cracking in bulk glasses may also play a role in the subcritical debonding behavior of multilayer interconnect structures. Accordingly, this work focuses on the effects of temperature and humidity on subcritical debonding and rationalizes them in terms of the relevant chemical reactions taking place at the debond tip.

Moisture diffusion along the TiN/SiO2 interface and in plasma-enhanced chemical vapor deposited SiO2

The diffusivity of moisture along the TiN/SiO2 interface has been determined by imaging the inward diffusion of 18O and 2D from isotopically labeled water using a secondary ion mass spectroscopy (SIMS) technique. The diffusivity, at room temperature, of the 18O and 2D labeled species along the interface are indistinguishable and have a value of 6.0±2.0×10−13 cm2/s, four orders of magnitude faster than bulk diffusivity of the same species in the plasma-enhanced chemical vapor deposition silica, also determined by SIMS. From 8 to 90 °C, the activation energies for interface and bulk diffusivities of the 2D labeled species are found to be 0.21 and 0.74 eV, respectively.

Performance of polycrystalline silicon waveguide devices for compact on-chip optical interconnection

Optical interconnects offer advantages over electrical interconnects in terms of clock skew, crosstalk, and RC delay for ULSI (Ultra Large Scale Integrated-Circuit) silicon technology. Optical interconnects are also applicable in optical communications where compact optical devices are fabricated and incorporated in an on-chip integrated optical system. Polycrystalline silicon (polySi)/SiO2 is an attractive waveguiding system that offers significant advantages in both applications with its compact size and compatibility with multilevel CMOS processing. Based on the process optimization that led to a low-loss polySi material, we have fabricated compact waveguide bends and splitters that were microns in size. To study the modal behavior in bending and splitting, we compared multi-mode and single-mode waveguides that were used in fabricating bends and splitters. Two waveguide cross-section dimensions, 0.5 micron X 0.2 micron and 2 microns X 0.2 microns, were used for single- mode waveguide and multi-mode waveguide, respectively. Micron- sized bending was realized with a low loss of a few dBs. Single-mode bends showed less than 3 dB loss for a bending radius of 3 microns, which was lower than that for multi-mode bends. Two different types of splitters, single-mode Y- splitters and multi-mode Y-splitters were fabricated and characterized in terms of their splitting uniformity. One X four and 1 X 16 optical power distribution systems were built based on different splitting schemes and their output power uniformity was compared. Due to the high dielectric contrast of our polySi/SiO2 waveguide system, the smallest 1 X 16 optical power distribution was realized in an area smaller than 0.0001 cm2.

The Energy Release Rate for Decohesion in Thin Multilayered Films on Substrates

The strain energy release rates for the converging decohesion crack in a multilayered film on a substrate have been calculated using the finite element method. The results for the energy release rate as a function of the intrinsic stress, the thickness of the superlayer and the modulus ratio will be presented. A simple functional form for the results will be shown. The effects of plasticity of the thin metal layer on the energy release rate have been examined. The results show that the effect of plastic deformation is not significant for the converging decohesion crack. The effects of the line width have also been addressed. The results show that for two-layer films the energy release rate for steady-state decohesion cracks decreases dramatically as B/h decreases, in the range B/h