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Dive into the research topics where Harry Q. Pon is active.

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Featured researches published by Harry Q. Pon.


international conference on solid state and integrated circuits technology | 2006

Technology scaling impact on NOR and NAND flash memories and their applications

Harry Q. Pon

NOR and NAND flash memories have scaled over 9 generations and 20 years since their 1986 product introductions. This scaling of both memory types in conjunction with MLC technology have enabled the cellular phone market and digital still camera market with high density code and removable data storage. This paper will discuss how flash technology scaling continues to enable new solutions for both the mobile communication and PC computing platforms. A new DDR NOR flash interface will enable high performance (133MHz and higher) code execution in mobile applications such as 3G/UMTS mobile phones. Non-volatile memory (NVM) disk caches are emerging as key and viable subsystem for the PC computing and other applications. The addition of NAND flash into the PC memory hierarchy delivers better performance, improved power savings and a richer user experience. Despite the challenges imposed by memory technology scaling, flash memory solutions will evolve to an ever changing variety of application needs with lower power, ever diversified and more efficient solutions


2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop | 2007

A NAND Flash PC Platform Read Write Cache

Harry Q. Pon; Kishore Rao

The traditional and ideal use of NAND flash has been primarily for the storage of digital images, music files, or data files in various memory cards types or USB keys. In this paper, a new non-volatile memory layer hierarchy is introduced into the PC computing platform as a NAND flash read write cache interfacing to the PCI express bus. The usage model of NAND flash in the consumer memory card environment is dramatically different from that of the PC computing environment. Consequently, the NAND flash PC platform cache usage model, work load analysis, reliability requirements and respective results was discussed.


international memory workshop | 2014

Reliability issues studied in Solid-State Drives

Harry Q. Pon; Justin R. Dayacap; Robert E. Frickey; Sireesha Gogineni; Peter Joseph; Eric Lin; Florence R. Pon; James P. Slattery

Solid-State Drives (SSDs) have impacted the computing platform and storage industry by providing substantially higher bandwidth random and sequential read write performance compared to Hard Disk Drives (HDDs). Due to these storage performance benefits, SSDs have also demanded more and stressed the NAND components beyond the typical usage models of removable storage media. In this work, several key SSD and NAND component reliability issues as the result of extra performance demands are examined in their respective forms. These include the effects of drive cycling with associated temperature bake, NAND component read disturb, NAND “XOR” (internal RAID), and SSD mechanical reliability issues. Data and results from these respective SSD reliability areas will be presented and discussed.


international conference on solid-state and integrated circuits technology | 2008

NAND flash read/write cache directions for the personal computing platform

Harry Q. Pon

In 2007, NAND flash memory was first introduced into the personal computing platform by Intel in the form of a non-volatile read/write cache to augment the PC computing platform memory subsystem. This innovation provided faster random access to key data and files instead of requiring access to the magnetic hard disk drive. In its introductory form, utilizing then available NAND flash memory generation and architecture, the NAND flash read/write cache performed well on a PCI-express bus. However, the PC computing platform is evolving to further utilize the benefits of NAND flash memory to enable a better user experience to include: faster hibernations and resumes; a virtual SATA SSD (Solid State Drive) partition; user controls to select which applications receive accelerated execution; and increased data access speed for frequented data. In this paper, the changing PC platform and the NAND flash architecture, performance demands, memory interfaces, and the heightened reliability usage model creating the new computer platforms will be discussed.


Archive | 1997

Self-configuring interface architecture on flash memories

Robert E. Larsen; Harry Q. Pon; Sanjay Talreja; Marcus E. Landgraf; Ranjeet Alexis


Archive | 1996

Self-calibrating address transition detection scheme

Harry Q. Pon


Archive | 2009

Wireless device content information theft protection system

Harry Q. Pon; Shawn Sackman


Archive | 2001

Insulated bond wire assembly for integrated circuits

Harry Q. Pon


Archive | 1997

Self-configuring input buffer on flash memories

Robert E. Larsen; Harry Q. Pon


Archive | 2005

Theft protection of a wireless device and content protection on the device

Harry Q. Pon; Shawn Sackman

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