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Dive into the research topics where Ranjeet Alexis is active.

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Featured researches published by Ranjeet Alexis.


international symposium on multiple valued logic | 2000

A multilevel-cell 32 Mb flash memory

Mark Bauer; Ranjeet Alexis; Greg Atwood; B. Baltar; Al Fazio; Kevin W. Frary; M. Hensel; Michel I. Ishac; Johnny Javanifard; Marcus E. Landgraf; D. Leak; K. Loe; Duane R. Mills; Paul D. Ruby; Rod Rozman; Sherif Sweha; Sanjay Talreja; Kenneth E. Wojciechowski

A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the first memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.


Archive | 1993

Special test modes for a page buffer shared resource in a memory device

Mickey L. Fandrich; Salim B. Fedel; Ranjeet Alexis; Mamun Ur Rashid


Archive | 1998

Flash memory partitioning for read-while-write operation

Peter K. Hazen; Ranjeet Alexis; Robert E. Larsen; Charles W. Brown; Sanjay Talreja


Archive | 1998

Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers

Ranjeet Alexis; Robert E. Larsen


Archive | 1997

Self-configuring interface architecture on flash memories

Robert E. Larsen; Harry Q. Pon; Sanjay Talreja; Marcus E. Landgraf; Ranjeet Alexis


Archive | 1997

Multiply and divide current mirror

Ranjeet Alexis


Archive | 1996

Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus

Rodney R. Rozman; Richard J. Durante; Mickey L. Fandrich; Ranjeet Alexis


Archive | 1998

Method and apparatus for placing a memory in a read-while-write mode

Ranjeet Alexis; Peter K. Hazen; Charles W. Brown; Robert E. Larsen


Archive | 1998

Self-compensating geometry-adjusted current mirroring circuitry

Ranjeet Alexis


Archive | 1998

Self-configuring 1.8 and 3.0 volt interface architecture on flash memories

Robert E. Larsen; Harry Q. Pon; Sanjay Talreja; Marcus E. Landgraf; Ranjeet Alexis

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