Ranjeet Alexis
Intel
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Ranjeet Alexis.
international symposium on multiple valued logic | 2000
Mark Bauer; Ranjeet Alexis; Greg Atwood; B. Baltar; Al Fazio; Kevin W. Frary; M. Hensel; Michel I. Ishac; Johnny Javanifard; Marcus E. Landgraf; D. Leak; K. Loe; Duane R. Mills; Paul D. Ruby; Rod Rozman; Sherif Sweha; Sanjay Talreja; Kenneth E. Wojciechowski
A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the first memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.
Archive | 1993
Mickey L. Fandrich; Salim B. Fedel; Ranjeet Alexis; Mamun Ur Rashid
Archive | 1998
Peter K. Hazen; Ranjeet Alexis; Robert E. Larsen; Charles W. Brown; Sanjay Talreja
Archive | 1998
Ranjeet Alexis; Robert E. Larsen
Archive | 1997
Robert E. Larsen; Harry Q. Pon; Sanjay Talreja; Marcus E. Landgraf; Ranjeet Alexis
Archive | 1997
Ranjeet Alexis
Archive | 1996
Rodney R. Rozman; Richard J. Durante; Mickey L. Fandrich; Ranjeet Alexis
Archive | 1998
Ranjeet Alexis; Peter K. Hazen; Charles W. Brown; Robert E. Larsen
Archive | 1998
Ranjeet Alexis
Archive | 1998
Robert E. Larsen; Harry Q. Pon; Sanjay Talreja; Marcus E. Landgraf; Ranjeet Alexis