Hartmud Terletzki

Scaling down and reliability problems of gigabit CMOS circuits

Abstract Scaling down of the current Megabit CMOS technology into the Gigabit range will be accompanied by a reduction of the operation voltage to limit the power consumption. This will compensate the scaling down of the oxide thickness so that the maximum electric field strength across the gate oxide can be kept approximately constant. Because of the increasing device density as well as number of MOS transistors per chip, the gate oxide area and the gate oxide perimeter length per chip will strongly increase, requiring a corresponding decrease of the defect density. The small structure size of the interconnects needs adjusted deposition and structuring techniques for the metal wiring and the intermetal dielectrics to increase the electromigration and stressmigration resistance.

Reliability problems of submicron MOS transistors and circuits

Abstract In this paper, the major reliability problems which occur in submicron MOS transistors and circuits are discussed. This comprises hot carrier degradation, oxide stability, latch-up, alpha particle hits, electrostatic discharge (ESD), and electromigration. The basic physical effects which can be detrimental to the device and circuit reliability are described and means to cope with them are explained. It is shown that, although devices with a very small structure size are much more susceptible to stress-related damage, the reliability does not necessarily decrease because countermeasures are possible.