Werner Reczek

Reliability of latchup characterization procedures

Three different well bias concepts are studied in detail under worst-case (power-on) conditions to evaluate the reliability of three distinct latchup characterization methods. An electrical method shows the most reliable results for the detection of latchup occurrence. A laser scanning method is the most reliable for localization of latchup susceptible regions. While the imaging of faint light is useful for detecting hot electrons and transistors in saturation, it is of little value for latchup observations.<<ETX>>

Critical charge model for transient latch-up in VLSI CMOS circuits

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches.<<ETX>>

Latch-up Free CMOS Using Buried Polysilicon Diodes

Latch-up free CMOS circuit operation is achieved through the use of buried polysilicon diodes instead of conventional (ohmic) well contacts. In a DRAM technolgy with polysilicon bit line a buried polysilicon diode can be realized with no additional process step and no additional die area is required. No degradition of MOS device parameters occurs. The basis for experiment is a 4M DRAM 0.9μm n-well CMOS technology with substrate bias generator [1].

Modelling the Field Soft Error Rate of DRAMs by varying the critical cell Charge

The Field Soft Error Rate (FSER) has been determined by the variation of the critical charge and the measurement of the charge collection volume determined by alpha-particle irradiation. The modelled FSER versus critical charge dependence agrees well to the one of the Field Soft Error measurements. The results futher show, that the impact of the on-chip Alpha-Particle flux can be neglected.

Scaling aspects for different CMOS circuit designs due to transient latch-up effects☆

Abstract The influence of three different scaling concepts: constant field (CE); constant voltage (CV); and compaction shrink (CS) on the latch-up behaviour of CMOS circuits is examined in detail for each of three circuit design methods: (1) floating well concept with substrate-bias (VBB) generator; (2) conventional LOGIC with grounded p-substrate and n-well connected to VCC; and (3) DRAM/LOGIC with VBB generator and n-well connected to VCC. Scaling results in increased power-on latch-up susceptibility for circuits with VBB generators. This risk can only be reduced by the use of protection circuits which limit the internal power supply ramp rate. Latch-up susceptibility to pulses (e.g. overshoot, undershoot and glitches) is increased for each circuit type as a result of scaling and can only be reduced by the use of novel device structures or by new and better developed technologies. For example, a highly doped substrate with a box isolation may be used, where the trench reaches far into the highly-doped region. The results presented are valid for both p-well and n-well concepts as the mechanism which initiates transient latch-up is independent of the well concept used.