Hartmut Penner

The GNU 64-bit PL8 compiler: toward an open standard environment for firmware development

For two decades, large parts of zSeries® firmware have been Written in the PL8 programming language. The existence of a large amount of mature zSeries firmware source code and our excellent experienee with PL8 for system programming suggest keeping this language. However, the firmware address space of todays, zSeries servers may exceed 2 GB, raising the need for a new 64-bit PL8 compiler, since the original implementation, developed at the IBM Thomas J. Watson Research Center, Yorktown Heihts, New York, supports only 32-bit platforms. The GNU compiler collection (GCC) (GNU is a freeware UNIX® -like operating system) has been used to translate those parts of firmware written in C for some years and has also proved successful in compiling LinuxTM for zSeries. This fact, combined with the highly modular GCC design, suggested reimplementing PL8 within the GCC framework. In this paper, we report on the extension of PL8 to support 64-bit addressing, its implementation as a GCC front end, and the validation of the new compiler. We also evaluate PL8 as a language for highly reliable low-level programming and give some performance data. The paper documents the high level of quality achieved by the GCC open-source project and how Such software fits into the traditional IBM software development processes.

Contributions to the GNU compiler collection

The GCC (GNU Compiler Collection) project of the Free Software Foundation has resulted in one of the most widespread compilers in use today that is capable of generating code for a variety of platforms. Since 1987, many volunteers from academia and the private sector have been working to continuously improve the functionality and quality of GCC. Some of the compilers key components were, and continue to be, developed at IBM Research laboratories. We review several of IBMs contributions to the compiler, including a code generator for the IBM zSeries® processor and a front end for a PL/I-like language used for systems software programming. We also cover many optimizations, including the interblock instruction scheduler, software pipeliner, and vectorizer. These contributions help improve the overall performance of code generated by GCC, and in particular, enhance the IBM RISC (reduced instruction set computer) architecture and the zSeries processors. This paper includes a report on our general experience with GCC in both open source and proprietary software environments and reviews the quality and performance of GCC-generated code.

Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications

This paper describes the hardware and software ecosystem encompassing the brain-inspired TrueNorth processor – a 70mW reconfigurable silicon chip with 1 million neurons, 256 million synapses, and 4096 parallel and distributed neural cores. For systems, we present a scale-out system loosely coupling 16 single-chip boards and a scale-up system tightly integrating 16 chips in a 4 × 4 configuration by exploiting TrueNorths native tiling. For software, we present an end-to-end ecosystem consisting of a simulator, a programming language, an integrated programming environment, a library of algorithms and applications, firmware, tools for deep learning, a teaching curriculum, and cloud enablement. For the scale-up systems we summarize our approach to physical placement of neural network, to reduce intra- and inter-chip network traffic. The ecosystem is in use at over 30 universities and government/corporate labs. Our platform is a substrate for a spectrum of applications from mobile and embedded computing to cloud and supercomputers.

Open-standard development environment for IBM System z9 host firmware

When the PL8 64-bit GNU compiler collection front end was introduced with the IBM z990 system, it laid the foundation to move toward an open-standard development environment for the i390 layer of IBM System zTM host firmware. However, when the z990 system was developed, the proprietary project development library system and the table of contents object file format for i390 code were still being used. With the IBM System z9TM, we have moved to a fully open-standard development environment. This paper describes the steps we took to get there, to improve code performance, development efficiency, and regression testing, and to develop base functionality for important System z9 features such as enhanced driver maintenance. We also discuss plans to further enhance the development environment for future systems.

A study in rapid prototyping: Leveraging software and hardware simulation tools in the bringup of system-on-a-chip based platforms

Traditional use of software and hardware simulators and emulators has been in efforts for chip level analysis and verification. However, prototyping and bringup requirements often demands system or platform level integration and analysis requiring new uses of these traditional pre-silicon methods along with novel interpretations of existing hardware to prototype some functions matching behaviors of future systems. In order to demonstrate the versatility and breadth of the pre-silicon environments in our systems lab, ranging from functional instruction set software simulators to Field Programmable Gate Array (FPGA) chip logic implementations to integrated systems of existing hardware built to mimic key functional aspects of the future platforms, we present our experiences with platform level verification, analysis and early software development/enablement for an I/O attached network appliance system. More specifically, we show how simulation tools along with these early prototype systems were used to do chip level verification, early software development and even system level software testing for a System on a Chip processor attached as an I/O accelerator via Peripheral Component Interconnect Express (PCI Express) to a host system. Our experiences demonstrate that leveraging the full range of pre-silicon environment capabilities results in full system level integrated software test for a I/O attached platform prior to the availability of fully functional ASICs.

directCell: hybrid systems with tightly coupled accelerators

The Cell Broadband Engine® (Cell/B.E.) processor is a hybrid IBM PowerPC® processor. In blade servers and PCI Express® card systems, it has been used primarily in a server context, with Linux® as the operating system. Because neither Linux as an operating system nor a PowerPC processor-based architecture is the preferred choice for all applications, some installations use the Cell/B.E. processor in a coupled hybrid environment, which has implications for the complexity of systems management, the programming model, and performance. In the directCell approach, we use the Cell/B.E. processor as a processing device connected to a host via a PCI Express link using direct memory access and memory-mapped I/O (input/output). The Cell/B.E. processor functions as a processor and is perceived by the host like a device while maintaining the native Cell/B.E. processor programming approach. We describe the problems with the current practice that led us to the directCell approach. We explain the challenge in programming, execution control, and operation on the accelerators that were faced during the design and implementation of a prototype and present solutions to overcome them. We also provide an outlook on where the directCell approach promises to better solve customer problems.

Design and Implementation of a Network Centric Appliance Platform

Increasing demands on end-to-end solution performance has lead to a generation of workload optimized systems and appliances, with tightly integrated hardware and software delivering substantial improvements over general purpose architectures. Among the many challenges encountered in designing an appliance, the most complex one is making hardware and software high performance and, at the same time, render the system versatile enough to support as many workloads as possible. This paper provides a high level overview of the design and implementation process of such an appliance architecture, as realized by the IBM PowerEN team. The platform includes new silicon (the PowerEN processor), a novel system level board (Chroma card), system software and development kit, as well as end user applications for different industry domains. The solution has been completely designed by the team, starting from concept, to architecture, to implementation and delivery. The paper describes the most important characteristics of the platform, detailing how these influence its capability of supporting multiple optimized workloads.