Catherine H. Crawford

eModel: addressing the need for a flexible modeling framework in autonomic computing

The paper describes a novel, flexible framework, eModel, designed to address the runtime requirements of autonomic computing: on-line workload measurement, analysis, and prediction. The eModel architecture has been developed using platform independent technology (XML and Java) to allow for maximum portability while also allowing for ease-of-integration with existing measurement and system management tools. The eModel toolkit consists of a GUI based model builder tool, a data base deployment tool, a runtime tool, and an analysis tool. In addition to the toolkit, the eModel design provides a runtime architecture which can be deployed directly without using any interaction with the GUI. The architecture is flexible enough to allow for incorporation with models of various complexity, including modeling techniques that require a hierarchical approach to attain reasonable accuracy based upon on-line, measured data. We present examples that illustrate eModel as a capacity planning tool as well as an augmentation to autonomic system management in an effort to highlight the technological gaps that the eModel framework is capable of bridging.

Commercial applications of grid computing

This paper provides an overview of commercial applications of Grid computing. We discuss Web performance and present a Grid caching architecture. Our Grid caching architecture offloads requests to Grid caches when Web servers become overloaded. We describe performance and traffic modeling techniques which can enhance Grid applications such as caching. We also discuss how Grid computing can be applied to financial applications. A key requirement here is that fast response times are needed. We present a Grid services scheduler that is well suited to commercial applications requiting fast response times.

Big Data: Cloud computing in genomics applications

Healthcare applications typically require big data management as well as intensive computation. This is especially true with recently developed next generation sequencing technology which increases interests in processing the huge amount of information in a timely fashion. In this paper, we focus on testing whether the healthcare applications can scale well on commercial big data platforms that implement MapReduce framework. We selected short read sequence alignment and assembly workloads in genome analysis workloads, and chose Bowtie, Blast and Contrail-bio which are publically available applications designed to run on the Hadoop MapReduce framework. To speed-up the processes we compressed the intermediate data using various compression schemes the compression schemes are compared. The test results are very promising and indicate that the wide range of genomic analysis workflows can be optimized on MapReduce frameworks with great computational efficiency and scalability.

A study in rapid prototyping: Leveraging software and hardware simulation tools in the bringup of system-on-a-chip based platforms

Traditional use of software and hardware simulators and emulators has been in efforts for chip level analysis and verification. However, prototyping and bringup requirements often demands system or platform level integration and analysis requiring new uses of these traditional pre-silicon methods along with novel interpretations of existing hardware to prototype some functions matching behaviors of future systems. In order to demonstrate the versatility and breadth of the pre-silicon environments in our systems lab, ranging from functional instruction set software simulators to Field Programmable Gate Array (FPGA) chip logic implementations to integrated systems of existing hardware built to mimic key functional aspects of the future platforms, we present our experiences with platform level verification, analysis and early software development/enablement for an I/O attached network appliance system. More specifically, we show how simulation tools along with these early prototype systems were used to do chip level verification, early software development and even system level software testing for a System on a Chip processor attached as an I/O accelerator via Peripheral Component Interconnect Express (PCI Express) to a host system. Our experiences demonstrate that leveraging the full range of pre-silicon environment capabilities results in full system level integrated software test for a I/O attached platform prior to the availability of fully functional ASICs.

Design and Implementation of a Network Centric Appliance Platform

Increasing demands on end-to-end solution performance has lead to a generation of workload optimized systems and appliances, with tightly integrated hardware and software delivering substantial improvements over general purpose architectures. Among the many challenges encountered in designing an appliance, the most complex one is making hardware and software high performance and, at the same time, render the system versatile enough to support as many workloads as possible. This paper provides a high level overview of the design and implementation process of such an appliance architecture, as realized by the IBM PowerEN team. The platform includes new silicon (the PowerEN processor), a novel system level board (Chroma card), system software and development kit, as well as end user applications for different industry domains. The solution has been completely designed by the team, starting from concept, to architecture, to implementation and delivery. The paper describes the most important characteristics of the platform, detailing how these influence its capability of supporting multiple optimized workloads.

Resource management with stateful support for analytic applications

Analytic applications from various industrial sectors have specific attributes and requirements including relatively long processing time, parallelization, multiple interactive invocations, Web services, and expected quality of service objectives. Current parallel resource management systems for batch-oriented jobs lack the effective support for multiple interactive invocations with consideration in quality of service objectives, while transaction processing systems do not support dynamic creation of parallel application instances. To better serve the analytic applications, a set of additional resource management services, defined as stateful support, introduces the concept of service instance and service instance management. This set of stateful support services can be implemented as extension to existing parallel resource management to serve these analytic applications that rapidly increase in the demand of computing power

High performance user space sockets on low power System on a Chip platforms

With the introduction of low power System on a Chip (SoC) processor architectures in enterprise server configurations, there is a growing need to develop the software that will support scale-out, data intensive cloud applications that are deployed in data centers today. In this paper, we describe the design and implementation of a low latency user space fully compliant TCP/IP socket stack on a low power System on a Chip (SoC) architecture and demonstrate that this library can become the basis for “Big Data” applications that require both high throughput and low latency capabilities all on a power optimized system platform. For our work, we are specifically targeting cloud applications that are developed on runtimes which are seeing great growth in programmer communities and enterprise deployment as well as for which the I/O bottlenecks outweigh the compute requirements, e.g. memcached. On low-power embedded-class SoC servers, these I/O bottlenecks can be prohibitively expensive for performance and scaling requirements of such applications, even when the CPU efficiency and memory bandwidth are adequate. Our approach removes this bottleneck by leveraging available SoC integrated Network Interface Cards (NICs) as well as user space communication - thereby improving pathlength to data as well as preserving CPU cycles from context switching. Our experiments show that we can achieve sub 5 μsec ping-pong latency for 8B packets, and also provide substantive improvement to the memslap benchmark not just when compared to memcached running on the T4240 with the kernel stack (3.5 times better for 16B SETs) but also when compared to a standard x86_64 server with ConnectX 10GbE adapters when power based metrics are used (close to a factor of 2 improvement with power normalized metrics).

Software architecture and system validation of an open, unified model for accelerated multicore computing

For systems that use hardware accelerators to combine multicore and multiprocess technology with libraries and computational kernels, the drawbacks are the complexity of the programming model and the corresponding verification of the software and validation of the system performance capabilities. In this paper, we describe a software approach to utilizing the compute power of the Cell Broadband Engine® processor and a cluster composed of x86-64 and IBM PowerXCell™ 8i processors integrated within a single hybrid compute node. We review past approaches to provide motivation for our development of the Data Communication and Synchronization (DaCS) library and Accelerated Library Framework (ALF), which enable developers to create new applications and adapt existing applications to exploit hybrid computing platforms. We follow with examples of porting existing x86-64 processor-based applications to the hybrid cluster platform in order to demonstrate the capabilities of ALF and DaCS and discuss how one application was extended to become a stress and performance test for various system components. Finally, we present the applicability of this programming model, accelerator design, and test architecture to other system architectures, applications, and workload segments.