Hartmut Ritter

Design and test of an integrated cryptochip

A self-testing cryptographic coprocessing chip that provides high security for any data protected through its use is described. The design philosophy and chip architecture are examined. Detailed design and test methods and solutions are given, and it is explained why the chips design interacts well in networks and with secure hard disks.<<ETX>>

Hearing aid with a directional microphone characteristic and method for producing same

In a method for producing a directional microphone characteristic and hearing aid device having a directional microphone characteristic, high-pass filters following two omnidirectional microphones are matched as to their limit frequencies for amplitude response and/or phase response of the two microphones. The limit frequency of the high-pass filter following one microphone is matched to the limit frequency of the other microphone.

Method and adapting a hearing aid, and hearing aid with a directional microphone arrangement for implementing the method

In a method for adapting a hearing aid, and a hearing aid arrangement for improving the directivity of a hearing aid with a number of microphones that are connected to one another for generating a directional characteristic, the hearing aid is exposed to acoustic waves in a room for precision measuring while the user is wearing it, and the directional characteristic is registered. The filter parameters that arise therefrom are supplied to parameterizable filters in the hearing aid that are connected downstream from the microphones, and the desired ideal directional characteristic can be approximated taking the individual conditions into account when the hearing aid is worn.

Complete self-test architecture for a coprocessor (cryptography)

A combination of a firmware-based and a hardware-based self-test architecture is chosen for the complete test of a coprocessor. The hardware approach is useful in testing completely embedded macrocells and supporting the self-test firmware, Four embedded macrocells were made self-testable by implementing well-known built-in self-test methods. The self-test architecture applied is of general applicability (linear feedback shift register). The remaining macrocells and the coordination of the various chip macrocells are tested by executing an on-chip firmware routine. By use of ordinary processor functions it is possible to reduce considerably the hardware overhead for implementing a complete self-test.<<ETX>>

Method and apparatus for level limitation in a digital hearing aid

For level limitation of a time-discrete signal in a digital hearing aid having at least an input transducer, an A/D converter, a signal processing unit and an output transducer, the sampling rate of the time-discrete signal is boosted in the signal path following the A/D conversion and signal values of the time-discrete signal with a boosted sampling rate are limited to a maximum value. Harmonics that arise upon limitation of the signal values that are folded back into the audible frequency range are thus suppressed.

Measurement and visualization of three‐dimensional directivity pattern

In order to optimize a new second‐order multimicrophone technology for a KEMAR dummy head, a three‐dimensional directivity measurement setup was developed. To minimize mechanical mass and to reduce total measurement time a C‐Bow setup was used, containing 18 calibrated loudspeakers. Those small tweeters identical in construction are placed in every 10 deg of elevation in a semicircular arc of 2‐m diameter. The only moving part of this setup is a full‐circle rotating KEMAR. The ANSI Standard 3.35 for directional measurement is fully supported and the required 48 measuring points are completed in less than 3 min. Using this fast and simple setup, the various responses attained from different latitudes need to be weighted to calculate a three‐dimensional directivity value. Utilizing an equally distributed number, for example 400 measuring points easily executable with this setup, weighting can be omitted and a three‐dimensional plot with high resolution can be visualized. Additionally, two‐dimensional cuts o...

Modular BIST concept for microprocessors

A concept of general usability of a complete self-test for microprocessors is shown by an example. A combination of a firmware-based and a hardware-based self-test architecture is chosen. The hardware approach is useful to test completely embedded macrocells and to support and minimize the self-test firmware. Four embedded macrocells are made self-testable by implementing well-known modular built-in self-test (BIST) methods. The self-test architecture applied is of general applicability. The remaining macrocells, as well as the coordination of the various chip macrocells, are tested by executing an on-chip firmware routine. By using the ordinary processor functions it is possible to considerably reduce the hardware overhead for implementing a complete self-test.<<ETX>>