Haruhiko Terada

Characterization of WID delay variability using RO-array test structures

Characterization of delay variability on a real silicon is one of key challenges for DFM&Y. We have measured D2D and WID delay variability in 65nm, 90nm, and 180nm processes using RO-array test structures, and decomposed WID variability into three components of random, deterministic, and systematic variation in descending order of magnitude for all three processes at a single-gate level.

Erect of regularity-enhanced layout on printability and circuit performance of standard cells

As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-or among manufacturability, cost, and performance for each process technology. This paper discusses the erect of layout regularity on printability and circuit performance in 90¿45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45nm process. We demonstrate the quantitative evaluation of the trade-or between printability and circuit performance of regularity-enhanced standard cells.

Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis

In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%.