Hidetoshi Onodera

Branch-and-bound placement for building block layout

We present a branch-and-bound placement technique for building block layout that effectively searches for an optimal placement in the whole solution space. We first describe a block placement problem and its solution space. Then we explain branching and bounding operations designed for the placement problem. Constraints on critical nets and/or the shape of a resulting chip can be taken into account in the search process. Experiments reveals that the number of blocks the method can manage is around six if the whole solution space is explored. For a problem which contains more blocks than the limit, we decompose the problem hierarchically and apply the method to each subproblem. The results for standard benchmark examples and a comparison with those of other systems are given to demonstrate the performance of the method.

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density. >

Manufacturability-Aware Design of Standard Cells

We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of gate-forming poly-silicon patterns as a measure for manufacturability, which is a major contributor of systematic gate-length variation. First, we study the ACLV of standard cell layouts by lithography simulation. Then, we introduce regularity in gate-forming poly-silicon patterns and how it improves the ACLV and also how it incurs area-overhead. According to the investigation, we propose two design guidelines for standard-cell layout that can reduce ACLV with reasonable area overhead. Those guidelines include on-grid fixed-pitch layout with dummy-poly insertion and stretched gate-poly extension. Design experiments assuming a 65 nm process technology indicate that a D-FF designed with the first guideline reduces ACLV by 35% with 14% area overhead and the second guideline reduces ACLV by 75% with 29% area overhead at the best focus condition. Under defocus conditions, both layouts exhibit stable characteristics whereas the variability of conventional layout grows rapidly as the level of defocus increases. Circuit-level lithography simulation over benchmark circuits also supports that the proposed guidelines considerably reduces the amount of gate length variation.

A cyclic A/D converter that does not require ratio-matched components

A successive-approximation analog-to-digital (A/D) converter is roost widely used for intermediate-speed applications. The circuit uses accurately ratio-matched components as a precision reference element. Hence, the analog portion of the converter cannot be easily scaled down. To overcome this problem, several circuits whose conversion characteristics do not depend on ratio accuracy have been proposed [1,2].

Refractive-index measurement of bulk materials: prism coupling method

A simple method of measuring refractive indices of bulk materials using a prism coupling procedure is described. Refractive indices are determined from the measurement of the angle incident to the prism at which total reflection on the prism base breaks. This method is shown to possess the advantages of its simple procedure and sample preparation. The accuracy is comparable with that of minimum deviation method if the prism is well calibrated. Experimental results for several materials are given with an evaluation of possible errors.

An efficient algorithm for layout compaction problem with symmetry constraints

An efficient algorithm is presented for the symbolic layout compaction problem with symmetry constraints. The symmetry constraint maintains the geometric symmetry of the circuit components during the layout compaction. It is indispensable to the symbolic layout for analog LSIs where the geometric symmetry between the components is important. However, it makes the compaction problem so complicated that no efficient algorithm has ever been shown except for the time-consuming linear programming algorithm. The proposed algorithm uses both the graph-based technique and the linear programming technique, and takes advantage of the high speed of the former and the generality of the latter. The authors implemented the proposed algorithm in a layout compaction program. The experimental results show that the proposed algorithm is fast enough for practical use.<<ETX>>

A Statistical Gate-Delay Model Considering Intra-Gate Variability

This paper proposes a model for calculating statistical gate-delayvariation caused by intra-chip and inter-chip variability. As thevariation of individual gate delays directly influences the circuit-delayvariation, it is important to characterize each gate-delay variationaccurately. Furthermore, as every transistor in a gate affectsthe transient characteristics of the gate, it is also necessary to considerthe intra-gate variability in the model of gate-delay variation.This effect is not captured in existing statistical delay analyses. Theproposed model considers the intra-gate variability through the introductionof sensitivity constants. The accuracy of the model isevaluated, and some simulation results for circuit delay variationare presented.

Variability : Modeling and its impact on design

As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in the design of integrated circuits. Besides the growing amount of variability, the statistical nature of the variability is changing as the progress of technology generation. In the past, die-to-die variability, which is well managed by the worst case design technique, dominates over within-die variability. In present and the future, the amount of within-die variability is increasing and it casts a challenge in design methodology. This paper first shows measured results of variability in three different processes of 0.35, 0.18, and 0.13μm technologies, and explains the above mentioned trend of variability. An example of modeling for the within-die variability is explained. The impact of within-die random variability on circuit performance is demonstrated using a simple numerical example. It shows that a circuit that is designed optimally under the assumption of deterministic delay is now most susceptible to random fluctuation in delay, which clearly indicates the requirement of statistical design methodology.

A performance optimization method by gate sizing using statistical static timing analysis

We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties due to local random fluctuation. Utilizing our method, over-design of a circuit can be eliminated and high-performance and high-reliability LSI design can be realized. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce delay and power dissipation from the circuits optimized without the consideration of fluctuation.

Variability modeling and impact on design

Measured variabilities from 0.35 mum to 90 nm processes are explained with a growing concern of within-die components. Variability impact on circuit performance is discussed. A possible approach for mitigating the variability is the introduction of layout regularity, and its effect is examined by test structures in a 90 nm process and lithography simulation in a 45 nm process.